ISD14B20
5. FUNCTIONAL DESCRIPTION
There are two operational modes: address trigger (
NORM
) and direct trigger (
MODE
). After a new
condition is selected on
NORM
/
MODE
, the power must be cycled to enable it.
5.1. A
DDRESS
T
RIGGER
(
NORM
) O
PERATION
The start address bits (
S0
,
S1
,
S2
&
S3
) and end address bits (
E0
,
E1
,
E2
&
E3
) are used
to access the memory location and they can divide the memory into a maximum of 16 slots. As
an example of I14B20, they are defined as follows:
S3
(
E3
)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
S2
(
E2
)
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S1
(
E1
)
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S0
(
E0
)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Row #
0
8
16
24
32
40
48
56
64
72
80
88
96
104
112
120
14B20
Duration [s]
0
1.25
2.50
3.75
5.00
6.25
7.50
8.75
10.00
11.25
12.50
13.75
15.00
16.25
17.50
18.75
5.1.1. Record (
REC
) Operation
•
•
Low active input, level-hold for level-trigger or falling edge for edge-trigger with debounce required.
For 8kHz sampling frequency, if
REC
is held at Low for a period equal to 1 sec or more, then level
recording is activated. However, if
REC
is pulsed Low for less than 1 sec, then edge-trigger recording
is initiated.
For 6.4kHz sampling frequency, if
REC
is held at Low for a period equal to 1.25 sec or more, then
level recording is activated. However, if
REC
is pulsed Low for less than 1.25 sec, then edge-trigger
recording is initiated.
Recording begins from the start address to end address and
LED
is on.
Recording ceases whenever
REC
returns to High in level-hold mode or a subsequent lower going
pulse appears while in edge-trigger mode or when end address is reached. Then an EOM marker is
written at the end of message. And
LED
is off.
Then the device will automatically power down.
This pin has an internal pull-up device.
Once
REC
is active, input on
FT
,
NORM
/
MODE
,
S0
,
S1
,
S2
,
S3
,
E0
,
E1
,
E2
or
E3
is
illegal.
•
•
•
•
•
•
-8-
Publication Release Date: October 9, 2007
Revision 0
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