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ISD1420S 参数 Datasheet PDF下载

ISD1420S图片预览
型号: ISD1420S
PDF下载: 下载PDF文件 查看货源
内容描述: [Speech Synthesizer With RCDG, 20s, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOIC-28]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管商用集成电路
文件页数/大小: 33 页 / 316 K
品牌: WINBOND [ WINBOND ]
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ISD1400 SERIES
PIN NAME
RECLED
PIN NO
FUNCTION
Record LED
: The
RECLED
output is LOW during a record
cycle. It can be used to drive an LED to indicate a record
25
cycle is in progress. In addition,
RECLED
pulses LOW
momentarily when an end-of-message is encountered in a
playback operation.
XCLK
26
External Clock
: The input has an internal pull-down device.
The ISD1400 is configured at the factory with an internal
sampling clock frequency that guarantees its minimum
nominal record/playback time. For instance, an ISD1420
operating within specification will be observed to always have
a minimum of 20 seconds of recording time. The sampling
frequency is then maintained to a variation of +2.25 percent
over the commercial temperature and operating voltage
ranges, while still maintaining the minimum specified
recording duration. This will result in some devices having a
few percent more than nominal recording time.
The Internal clock has a +5 percent tolerance over the
industrial temperature and voltage range. A regulated power
supply is recommended for industrial temperature parts. If
greater precision is required, the device can be clocked
through the XCLK pin as follows:
EXTERNAL CLOCK SAMPLE RATES
Part Number
ISD1416
ISD1420
Sample Rate
8.0 kHz
6.4 kHz
Required Clock
1024 kHz
819.2 kHz
These recommended clock rates should not be varied
because the antialiasing and smoothing filters are fixed, and
aliasing problems can occur if the sample rate differs from the
one recommended. The duty cycle on the input clock is not
critical, as the clock is immediately divided by two.
If the
XCLK is not used, this input must be connected to
ground.
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