— Multiplexed address-data lines:
■ Four direct address lines
Features
System Health Support
■ Partial non-multiplexed option
■ SensorPath interface to sensors optimizes digital/ana-
— Four chip-select outputs, each supporting multiple
log partitioning
zones:
— Simplifies board design and routing
■ Two BIOS memory zones (up to 32 Mbytes total)
— Supports distributed sensors and centralized control
— Off-loads SMBus, faster boot time
■ Two user-defined memory zones
(up to 32 Mbytes total)
■ Four user-defined I/O zones
■ Fan Monitor and Control (FMC)
— Address line forcing (to 0 or 1) for access to two
— Four PWM-based fan controls
BIOS code and data sets
— Eight 16-bit resolution tachometer inputs
— Software or local temperature feedback control
— Optional indirect addressing of memory
— XRD-XEN or XWR-XR/W mode support
— Supports both slow and fast devices
■ Chassis intrusion detection
— For faster transactions in 16-bit data bus, strobe sig-
nals for address latches change automatically only
when the address is changed
Bus Interfaces
■ LPC Bus Interface
— Based on Intel’s LPC Interface Specification Revi-
sion 1.1, August, 2002
■ Configuration Control
— Compliant with PC2001 Specification Revision 1.0,
— Synchronous cycles using up to 33 MHz bus clock
— 8-bit I/O and 8-bit Memory read and write cycles
— Up to four 8-bit DMA channels
1999-2000
— Compliant with Hardware Design Guide Version 3.0
for Microsoft Windows 2000 Server, June 30 2000
— Serial IRQ
— Plug and Play (PnP) Configuration register structure
— Supports bootable memory
— Base Address strap, to setup the address of the
Index-Data register pair
— Supports LPC and FWH boot transactions
— Supports registers memory and I/O mapping
— Flexible resource allocation for all logical devices:
■ Relocatable base address
■ SMBus Interface
■ 15 IRQ routing options to serial IRQ
■ Up to four optional 8-bit DMA channels
— Compliant with SMBus Specification Revision 2.0,
August 3, 2000
— Enables a system controller to access the internal
— SMBus control over pin multiplexing, module disable
and output TRI-STATE® for all Legacy modules
functions and the fast X-Bus extension
— Proprietary commands for read/write byte from/to:
■ Internal register
Legacy Modules
■ X-Bus I/O device
■ Serial Ports 1 and 2
■ X-Bus memory device
— Software compatible with the 16550A and the 16450
— Supports shadow register for write-only bit monitoring
— UART data rates up to 1.5 Mbaud
— Three sets of Serial Interface pins
■ Serial Interface 1
— Slave address:
■ One of two values selected by strap
■ Programmable through the LPC bus
■ VBAT backed-up
■ Snoop or Take-over connection of Serial Inter-
— Supports SMBALERT
face M
— Concurrent access with the LPC bus
— VSB powered
■ Two-to-one multiplexing of Serial Ports 1 and 2 to
Serial Interface 2
— Optional internal pull-up on the two SMBus pins
■ Floppy Disk Controller (FDC)
— Programmable write protect
— Supports FM and MFM modes
■ Fast X-Bus Extension
— Supports I/O and memory read/write operations
— 8- or 16-bit data bus, 28-bit addressing
— Accessible from both LPC bus and SMBus
— VSB powered
— Supports Enhanced mode command for three-mode
Floppy Disk Drive (FDD)
— Perpendicular recording drive support for 2.88 MB
— Burst and Non-Burst modes
— Boot configuration selected by straps
— Programmable protection control for access from the
— Full support for IBM Tape Drive Register (TDR) im-
LPC bus
plementation of AT and PS/2 drive types
— Supports three XIRQ external interrupts
— 16-byte FIFO
— Error-free handling of data overrun and underrun
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