BRIGHT
Microelectronics
Inc.
Preliminary BM29F400T/BM29F400B
BLOCK DIAGRAM
DQ0-DQ15
Vcc
Vss
RY/BY
Buffer
Erase Boltage
Generator
Input/Output
Buffers
State
Control
/WE
/BYTE
/RESET
Command
Register
PGM Voltage
Generator
STB
Chip Enable
/CE
/OE
Output Enable
Data Latch
Logic
STB
Y-Gating
Y-Decodor
Cell Matrix
Vcc Detector
Address
Latch
Timer
X-Decoder
A0-A16
A-1
BUS OPERATION
(1)
Table 1. Bus Operations (BYTE = VIH)
OPERATION
A0
A1
A6
A9
DQ0-DQ15
CE
WE
RESET
OE
(2)
Electronic ID Manufacturer
L
L
H
H
H
X
X
H
L
L
L
L
VID
VID
A9
X
Code
Code
DOUT
H
H
H
H
L
(2)
Electronic ID Device
L
L
H
X
L
L
L
X
L
H
A0
X
L
L
(3)
Read
L
A1
X
A6
X
Standby
X
X
H
H
L
High Z
High Z
Hardware Reset
Output Disable
Write
X
X
X
X
X
X
X
X
High Z
DIN(4)
X
A0
L
A1
H
X
A6
L
A9
VID
X
H
H
VID
(2)
Verify Sector Protect
H
X
Code
X
Temporary Sector Unprotect
X
X
X
Notes:
1. L = VIL, H = VIH, X = Don't Care. See DC Characteristics for voltage levels.
2. Manufacturer and device codes may also be accessed via a command register sequence. Refer to Table 6.
3. WE can be VIL if is VIL, OE at VIH initiates the write operations.
CE
4. Refer to Table 6 for valid D during a write operation.
IN
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