ISD5100 – SERIES
Digital data is sent and received serially over the I2C interface. The data is serial-to-parallel converted
and stored in one of two alternating (commutating) 64-bit shift registers. When an input register is full,
it becomes the register that is parallel written into the array. The prior write register becomes the new
serial input register. A mechanism is built-in to ensure there is always a register available for storing
new data.
Storing data in the memory is accomplished by accepting data one byte at a time and issuing an
acknowledge. If data is coming in faster than it can be written, the chip issues an acknowledge to the
host microcontroller, but holds SCL LOW until it is ready to accept more data. (See section 7.5.2 for
details).
The read mode is the opposite of the write mode. Data is read into one of two 64-bit registers from the
array and serially sent to the I2C interface. (See section 7.5.3 for details).
7.3. OPERATIONAL MODES DESCRIPTION
7.3.1. I2C Interface
To use more than four ISD5100 Series devices in an application requires some external switching of
the I2C interface.
I2C interface
Important note: The rest of this data sheet will assume that the reader is familiar with the
I2C serial interface. Additional information on I2C may be found in section 10 on page 72 of
this document. If you are not familiar with this serial protocol, please read this section to
familiarize yourself with it. A large amount of additional information on I2C can also be
found on the Philips web page at http://www.philips.com/.
I2C Slave Address
The ISD5100 Series have 7-bit slave address of <100 00xy> where x and y are equal to the state,
respectively, of the external address pins A1 and A0. Because all data bytes are required to be 8
bits, the LSB of the address byte is the Read/Write selection bit that tells the slave whether to transmit
or receive data. Therefore, there are 8 possible slave addresses for the ISD5100-Series. These
are:
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