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WCSS0232V1P-75AC 参数 Datasheet PDF下载

WCSS0232V1P-75AC图片预览
型号: WCSS0232V1P-75AC
PDF下载: 下载PDF文件 查看货源
内容描述: 64K ×32的同步流水线高速缓存RAM [64K x 32 Synchronous-Pipelined Cache RAM]
分类和应用: 内存集成电路静态存储器时钟
文件页数/大小: 14 页 / 373 K
品牌: WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
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WCSS0232V1P  
Write Cycle Descriptions[4,5,6]  
Function  
Read  
GW  
1
BWE  
1
BW3  
X
1
BW2  
X
1
BW1  
X
1
BW0  
X
1
Read  
1
0
Write Byte 0 - DQ[7:0]  
Write Byte 1 - DQ[15:8]  
Write Bytes 1, 0  
Write Byte 2 - DQ[23:16]  
Write Bytes 2, 0  
Write Bytes 2, 1  
Write Bytes 2, 1, 0  
Write Byte 3 - DQ[31:24]  
Write Bytes 3, 0  
Write Bytes 3, 1  
Write Bytes 3, 1, 0  
Write Bytes 3, 2  
Write Bytes 3, 2, 0  
Write Bytes 3, 2, 1  
Write All Bytes  
1
0
1
1
1
0
1
0
1
1
0
1
1
0
1
1
0
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
0
0
1
0
0
1
1
1
1
0
0
1
1
0
1
0
0
1
0
1
1
0
0
1
0
0
1
0
0
0
1
1
1
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
Write All Bytes  
0
X
X
X
X
X
Current into Outputs (LOW) ........................................ 20 mA  
Maximum Ratings  
Static Discharge Voltage .......................................... >2001V  
(per MIL-STD-883, Method 3015)  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Latch-Up Current.................................................... >200 mA  
Storage Temperature ..................................... −65°C to +150°C  
Ambient Temperature with  
Power Applied.................................................. −55°C to +125°C  
Operating Range  
Ambient  
Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V  
Range Temperature[8]  
VDD  
VDDQ  
DC Voltage Applied to Outputs  
in High Z State[7] .....................................−0.5V to VDDQ + 0.5V  
Com’l  
0°C to +70°C  
3.3V  
5%/+10%  
3.3V  
5%/+10%  
DC Input Voltage[7]..................................−0.5V to VDDQ + 0.5V  
Notes:  
4. X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW.  
5. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW[3:0]. Writes may occur only on subsequent clocks  
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is  
a “don't care” for the remainder of the write cycle.  
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ=High-Z when OE is inactive or  
when the device is deselected, and DQ=data when OE is active.  
7. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.  
8.  
TA is the case temperature.  
6