WCMA1008C1X
Switching Characteristics[4] Over the Operating Range
55
70
Parameter
Description
Min.
55
5
Max.
Min.
70
5
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
ns
ns
ns
tAA
Address to Data Valid
55
70
tOHA
Data Hold from Address
Change
tACE
CE1 LOW to Data Valid, CE2
HIGH to Data Valid
55
20
70
35
ns
tDOE
OE LOW to Data Valid
OE LOW to Low Z[5]
OE HIGH to High Z[5, 6]
ns
ns
ns
ns
tLZOE
tHZOE
tLZCE
0
5
0
5
20
20
25
25
CE1 LOW to Low Z, CE2
HIGH to Low Z[5]
tHZCE
tPU
CE1 HIGH to High Z, CE2
LOW to High Z[5, 6]
ns
ns
ns
CE1 LOW to Power-Up, CE2
HIGH to Power-Up
0
0
tPD
CE1 HIGH to Power-Down,
CE2 LOW to Power-Down
55
70
WRITE CYCLE[7]
tWC
Write Cycle Time
55
45
70
60
ns
ns
tSCE
CE1 LOW to Write End, CE2
HIGH to Write End
tAW
tHA
Address Set-Up to Write End
45
0
60
0
ns
ns
Address Hold from Write
End
tSA
Address Set-Up to Write
Start
0
0
ns
tPWE
tSD
WE Pulse Width
45
25
0
50
30
0
ns
ns
ns
ns
ns
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[5, 6]
WE LOW to High Z[6]
tHD
tLZWE
5
5
tHZWE
20
25
Notes:
4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the
specified IOL/IOH and 100-pF load capacitance.
5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. The internal write time of the memory is defined by the overlap of CE1 LOW and CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate
a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal
that terminates the write.
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WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
