S1008V1C
WCFS1008V1C
128K x 8 Static RAM
Features
• High speed
— t
AA
= 12ns
• CMOS for optimum speed/power
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location speci-
fied on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The WCFS1008V1C is available in standard 400-mil-wide
package.
Functional Description
The WCFS1008V1C is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory expan-
sion is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and three-state drivers. This device
has an automatic power-down feature that significantly reduc-
es power consumption when deselected.
Logic Block Diagram
Pin Configurations
SOJ
Top View
A
0
A
1
A
2
A
3
CE
I/O
0
I/O
1
V
CC
V
SS
I/O
2
I/O
3
WE
A
4
A
5
A
6
A
7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
16
A
15
A
14
A
13
OE
I/O
7
I/O
6
V
SS
V
CC
I/O
5
I/O
4
A
12
A
11
A
10
A
9
A
8
I/O0
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
I/O1
ROW DECODER
I/O2
SENSE AMPS
512 x 256 x 8
ARRAY
I/O3
I/O4
I/O5
I/O6
CE
WE
OE
COLUMN
DECODER
POWER
DOWN
I/O7
Selection Guide
WCFS1008V1C 12ns
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
12
160
5
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
Revised April 19, 2002
WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
