Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
23,56,24, DQM0- Input Data Input/Output Mask: DQM0-DQM3 are byte specific, nonpersistent I/O buffer
57
DQM3
controls. The I/O buffers are placed in a high-z state when DQM is sampled HIGH.
Input data is masked when DQM is sampled HIGH during a write cycle. Output data
is masked (two-clock latency) when DQM is sampled HIGH during a read cycle.
DQM3 masks DQ31-DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8,
and DQM0 masks DQ7-DQ0.
97,98,100, DQ0-
Input/ Data I/O: The DQ0-31 input and output data are synchronized with the positive
1,3,4,6,7, DQ31 Output edges of CLK. The I/Os are byte-maskable during Reads and Writes. The DQs also
60,61,63,
64,68,69,
71,72,9,
serve as column/byte mask inputs during Block Writes.
10,12,13,
17,18,20,
21,74,75,
77, 78,80,
81, 83, 84
30,36-45,
52,58,
NC
-
No Connect: These pins should be left unconnected.
86-95
2,8,14,22, VDDQ Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
59,67,73,
79
5,11,19,
62,70,76,
82,99
VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
15,35,65,
96
VDD
VSS
Supply
Power Supply: +3.3V ±0.3V
16,46,66,
85
Supply Ground
Document:
Rev.1
Page4
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
