Preliminary
VG36641641BT
CMOS Synchronous Dynamic RAM
VIS
2.Truth Table
2.1 Command Truth Table
CKE
n - 1
A11
A9 - A0
FUNCTION
Device deselect
No operation
Symbol
DESL
NOP
n
X
X
X
X
X
X
X
X
X
X
X
H
L
CS
H
L
RAS CAS WE
BA
X
X
L
A10
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
X
H
L
X
H
L
X
H
L
X
X
V
V
V
V
V
V
X
X
X
X
X
Mode register set
Bank activate
MRS
L
ACT
L
L
H
L
H
H
H
L
V
V
V
V
V
V
X
X
X
X
V
L
Read
READ
READA
WRIT
WRITA
PRE
L
H
H
H
H
L
Read with auto precharge
Write
L
L
H
L
L
L
Write with auto precharge
Precharge select bank
Precharge all banks
Burst stop
L
L
L
H
L
L
H
H
H
L
L
PALL
BST
L
L
L
H
X
X
X
L
H
L
L
CBR (Auto) refresh
Self refresh
REF
L
H
H
SELF
L
L
L
2.2 DQM Truth Table
CKE
DQM
FUNCTION
Data write/output enable
Data mask/output disable
Symbol
n -1
H
n -1
X
U
L
ENB
MASK
ENBU
ENBL
L
H
X
H
Upper byte write enable/output enable
Lower byte write enable/output enable
Upper byte write inhibit/output disable
Lower byte write inhibit/output disable
H
X
L
X
H
X
X
L
H
X
MASKU
MASKL
H
X
X
H
H
X
2.3 CKE Truth Table
CKE
Add -
ress
Current State
Activating
Any
Function
Symbol
n - 1
n
CS
RAS CAS
WE
Clock suspend mode entry
Clock suspend
H
L
L
L
X
X
X
L
X
X
X
L
X
X
X
L
X
X
X
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
Clock suspend
Idle
Clock suspend mode exit
CBR refresh command
Self refresh entry
L
H
H
L
REF
H
H
L
Idle
SELF
L
L
L
Self refresh
Self refresh exit
H
H
L
L
H
X
X
X
H
X
X
X
L
H
X
X
Idle
Power down entry
Power down exit
H
L
Power down
H
H : High level, L : Low level
X : High or Low level (Don’t care), V : Valid Data input
Document : 1G5-0127
Rev2
Page9
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