Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
VIS
A.C Characteristics : (Ta = 0 to 70°C V = 3.3V ± 0.3V, V = 0V)
DD
SS
Parameter
CAS
Latency
VG3664321 (4) 1 (2) B
-8L
Unit
-8H
Max
-10
symbol
Min
Min
Max
Min
Max
CLK cycle time (1)
3
2
3
2
tck3
tck2
tAc3
tAc2
tCH
8
10
8
12
10
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK to valid output delay
6
6
6
6
6
6
CLK high pulse width
CLK low pulse width
CKE setup time
3
3
2
1
2
1
2
1
2
3
3
2
1
2
1
2
1
2
3
3
3
1
3
1
3
1
3
tCL
tCKS
tCKH
tAS
CKE hold time
Address setup time
Address hold time
Command setup time
Command hold time
Data input setup time
tAH
tCMS
tCMH
tDS
Data input hold time
tDH
1
1
1
ns
Output data hold time
CLK to output in low - Z
CLK to output in Hi - Z
tOH
tLZ
tHZ
3
0
3
0
3
0
ns
ns
ns
3
2
6
6
6
6
6
6
CLK to output in Hi - Z without load
tOHN
1
1
2
ns
Row active to active delay
RAS to CAS delay
Row precharge time
ROW active time
ROW cycle time
Last data in to burst stop
tRRD
tRCD
tRP
tRAS
tRC
16
20
20
48
70
1
16
20
20
48
70
1
20
26
26
60
90
1
ns
ns
ns
ns
ns
120K
120K
120K
tBDL
CLK
Data - in to ACT(REF) command
Data - in to precharge
Transition time
tDAL 1+ tRP
1+ tRP
1+ tRP
10
1
0.2
2
1
CLK
ns
ns
tD(P1L)
tT(2)
tT
tRSC
tSRX
tREF
8
1
0.2
2
8
1
0.2
2
10
5
10
5
10
5
Mode reg. set cycle
Self refresh exit time
Refresh time
CLK
CLK
ms
1
1
64
64
64
Notes : (1) The input clock should be stable and continuous. (jitter £ 7% * t
)
CK
Document : 1G5-0099
Rev.1
Page8
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
