Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
VIS
Note:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
2. All voltages are referenced to V
.
SS
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of t
CK
and t . Input signals are changed one time during t . Assume that there are only one read/write cycle during t (min).
RC
CK
RC
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Assume minimum column address update cycle t
(min).
CCD
6. Power-up sequence is described in Note 10.
7. A.C. Test Conditions
Reference Level of Output Signals
Output Load
1.4V / 1.4V
Reference to the Under Output Load (B)
Input Signal Levels
3.0V / 0.0V
1ns
Transition Time (Rise and Fall) of Input Signals
Reference Level of Input Signals
1.4V
3.3V
1.4V
1.2KW
50
W
ZO=50
W
Output
Output
30pF
30pF
870
W
LVTTL D.C. Test Load (A)
LVTTL A.C. Test Load (B)
8. Transition times are measured between V and V . Transition (rise and fall) of input signals are fixed slope (1 ns).
IH
IL
9. t defines the time at which the outputs achieve the open circuit condition and are not reference levels.
HZ
10. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to V and V
(simultaneously) when all input signals are held “NOP” state and
DD
DDQ
CKE = ”H”, DQM = ”H”. The CLK signals must be started at the same time.
2) After power-up, a pause of 200u secouds minimum is required. Then, it is recommended that DQM is held
“high” (V
levels) to ensure DQ output to be in the high impedance.
DD
3) Both banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
Document:1G5-0160
Rev.1
Page 7
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
