VG26(V)(S)18165C
1,048,576 x 16 - Bit
CMOS Dynamic RAM
VIS
TRUTH TABLE
ADDRESSES
FUNCTION
ROW
X
COL
X
DQS
RAS
H
LCAS
UCAS
WE
X
OE
X
Notes
STANDBY
High-Z
H ® X
H ® X
READ : WORD
L
L
L
L
L
H
H
L
L
ROW
ROW
COL
COL
Data-Out
READ : LOWER BYTE
H
Lower Byte: Data-Out
Upper Byte: High-Z
READ: UPPER BYTE
L
L
L
L
H
L
L
L
H
L
L
H
L
L
L
L
X
X
X
ROW
ROW
ROW
ROW
COL
COL
COL
COL
Lower Byte: High-Z
Upper Byte: Data-Out
WRITE: WORD
(EARLY WRITE)
Data-In
WRITE: LOWER
BYTE (EARLY)
L
Lower Byte: Data-In
Upper Byte: High-Z
WRITE : UPPER
BYTE (EARLY)
H
L
Lower Byte: High-Z
Upper Byte: Data-In
READ WRITE
L
L
L
L
L
L
L
ROW
ROW
n/a
COL
COL
COL
COL
COL
COL
COL
COL
COL
Data-Out, Data-In
Data-Out
1,2
2
H ® L L ® H
PAGE-MODE
READ
1st Cycle
H
H
L
L
L
H ® L
H ® L
H ® L
H ® L
H ® L
H ® L
H ® L
H ® L
H ® L
H ® L
2nd Cycle
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
READ
Data-Out
2
PAGE-MODE
WRITE
X
X
ROW
n/a
Data-In
1
L
Data-In
1
PAGE-MODE
READ-
WRITE
ROW
n/a
Data-Out, Data-In
Data-Out, Data-In
Data-Out
1,2
1,2
2
H ® L L ® H
H ® L L ® H
H ® L
H ® L
HIDDEN
L
L
H
L
L
ROW
ROW
L ® H ® L
REFRESH
WRITE
L
L
X
Data-In
1,3
L ® H ® L
L
RAS-ONLY REFRESH
CBR REFRESH
H
L
H
L
X
H
X
X
ROW
X
n/a
X
High-Z
High-Z
4
H ® L
Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (LCAS or UCAS).
Document:1G5-0147
Rev.1
Page4
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
