128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
BLOCK DIAGRAM
DQ0-7
I/O Buffer
Memory Array
4096 x1024 x8
Cell Array
Memory Array
4096 x1024 x8
Cell Array
Memory Array
4096 x1024 x8
Cell Array
Memory Array
4096 x1024 x8
Cell Array
Bank #0
Bank #1
Bank #2
Bank #3
Mode
Register
Control Circuitry
Address Buffer
Control Signal Buffer
Clock Buffer
/CS
/RAS
/WE
A0-11
CLK
CKE
/CAS
DQM
BA0,1
Note:This figure shows the P2V28S30ATP
The A2V28S20ATP configuration is 4096x2048x4 of cell array and DQ0-3
The A2V28S40ATP configuration is 4069x512x16 of cell array and DQ0-15
Type Designation Code
A
P2 V 28 S 3 0
TP -8
Access Item
-7 : 7 ns (143MHz/3-3-3)
-75 : 7.5ns (100MHz/2-2-2 or 133MHz/3-3-3)
-8 : 8 ns (100MHz/2-2-2 or 125MHz/3-3-3)
TP : TSOP(II)
Package Type
Process Generation
Function
A : 2nd generation
0 : Random Column
2 : x4, 3:x8, 4: x16
Organization
Synchronous DRAM
Density
128 :128Mbit
V :LVTTL
Interface
PSC DRAM
JULY.2000
Rev.2.2
Page-3
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
