DCM4623xD2K04A5yzz
High Level Functional State Diagram
Conditions that cause state transitions are shown along arrows. Sub-sequence activities listed inside the state bubbles.
Application of
V
IN
V
IN
> V
IN-INIT
INITIALIZATION
SEQUENCE
t
INIT
delay
Powertrain: Stopped
FT = True
EN = False
t
MIN-OFF
delay
NON LATCHED
FAULT
t
OFF
Powertrain: Stopped
FT = True
STANDBY
Powertrain: Stopped
FT = True
EN = True and
No Faults
t
ON
delay
EN = False
t
OFF
delay
SOFT START
V
OUT
Ramp Up
t
ss
delay
Powertrain: Active
FT = False
RUNNING
t
SS
Expiry
Regulates V
OUT
Powertrain: Active
FT = False
Ou
tpu
tO
VP
Powertrain: Stopped
FT = True
Fault Removed
NON LATCHED
FAULT
t
FAULT
Powertrain: Stopped
FT = True
LATCHED
FAULT
Ov
e
Ou r-tem
tpu
p
t U or
VP
REINITIALIZATION
SEQUENCE
t
INIT
delay
EN = False
DCM™ DC-DC Converter
Page 9 of 25
Rev 1.2
07/2017
In
p
In ut O
pu V
tU L
VL O o
O r
O
pu
ut
tO
VP
Powertrain: Stopped
FT = True
V
IN
> V
IN-UVLO+
and
not Over-temp
TR mode latched
EN = False
t
OFF-MIN
delay
ult
Fa oved
m
Re
or
O
VL O
O VL
ut t U
np pu
I n
I
or
mp
r-te
P
Ove put UV
Out
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