V•I Chip Bus Converter Module
Application Note (continued)
Input reflected ripple
measurement point
F1
7 A
Fuse
+Out
-Out
Notes:
+In
+
Load
–
Enable/Disable Switch
Source inductance should be no more than 200 nH. If source inductance is
greater than 200 nH, additional bypass capacitance may be required.
R3
10 mΩ
TM
C1
47 µF
electrolytic
BCM
R2
RSV
C3 should be placed close to the load.
2 kΩ
PC
C3
30 µF
+Out
D1
SW1
R3 may be ESR of C3 or a separate damping resistor.
D1 power good indicator will dim when a module fault is detected.
K
Ro
-In
-Out
Figure 20 — BCM test circuit
V•I Chip Bus Converter Level 1 DC Behavioral Model for 48 V to 8 V, 240 W
ROUT
IOUT
+
7.5 mΩ
+
1/6 • Iout
1/6 • Vin
•
V I
+
–
+
–
VOUT
VIN
I
67 mA
K
–
–
©
Figure 21 — This model characterizes the DC operation of the V•I Chip bus converter, including the converter transfer function and its losses. The model enables
estimates or simulations of output voltage as a function of input voltage and output load, as well as total converter power dissipation or heat generation.
V•I Chip Bus Converter Level 2 Transient Behavioral Model for 48 V to 8 V, 240 W
0.7 nH
Lout 1.6 nH
ROUT
IOUT
IN
L
= 5 nH
+
7.5 mΩ
+
RCOUT
RCIN
2.7 mΩ
1/6 • Vin
V•I
K
0.2 mΩ
48 µF
1.3 mΩ
1/6 • Iout
+
–
+
–
3.6 µF
CIN
COUT
VOUT
VIN
IQ
67 mA
–
–
©
Figure 22 — This model characterizes the AC operation of the V•I Chip bus converter including response to output load or input voltage transients or steady state
modulations. The model enables estimates or simulations of input and output voltages under transient conditions, including response to a stepped load with or
without external filtering elements.
vicorpower.com
800-735-6200
V•I Chip Bus Converter Module
B048F080T24
Rev. 2.1
Page 11 of 12
VICOR [ VICOR CORPORATION ]
