VL-FS-MDLS16166D-01 REV. A
(MDLS16166(33)-LV-G-LED01G (DIE FORM IC))
JAN./2002
PAGE 9 OF 12
4.3 Timing Specifications
At Ta = 0 °C To +50 °C , VDD = +5V 5%, VSS = 0V.
Refer to Fig. 2, the bus timing diagram for write mode.
Table 6
Parameter
Symbol
tCYCE
tWHE
tRE
Min.
500
300
-
Max.
Unit
ns
Remarks
Enable cycle time
-
-
Enable ”High” level pulse width
Enable rise time
ns
25
25
-
ns
Enable fall time
tFE
-
ns
RS, R/W set-up time
tAS
60
ns
8-bit operation mode
4-bit operation mode
100
10
RS, R/W address hold time
Data output delay
Data hold time
tAH
tDS
tDHR
-
-
-
ns
ns
ns
100
10
Refer to Fig. 3, the bus timing diagram for read mode .
Table 7
Parameter
Symbol
tCYCE
tWHE
tRE
Min.
500
300
-
Max.
Unit
ns
Remarks
Enable cycle time
-
-
Enable ”High” level pulse width
Enable rise time
ns
25
25
-
ns
Enable fall time
tFE
-
ns
RS, R/W set-up time
tAS
60
100
10
-
ns
8-bit operation mode
4-bit operation mode
RS, R/W address hold time
Read data output delay
Read data hold time
tAH
tRD
tDHR
-
190
-
ns
ns
ns
20
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