VL-FS- MDLS16119D-01 REV. A
(MDLS16119D-LV-DIE IC)
OCT/2001
PAGE 9 OF 12
4.3 Timing Specifications
At Ta = 0 °C to +50 °C , VDD = 5V±5% ,VSS = 0V.
Refer to Fig. 2 , the bus timing diagram for write mode.
Table 6
Parameter
Enable cycle time
Enable ”High” level pulse width
Enable rise time
Enable fall time
RS, R/W set-up time
Symbol
tCYCE
tWHE
tRE
Min.
500
300
-
-
60
100
10
100
10
Max.
Unit
ns
ns
ns
ns
Remarks
-
-
25
25
-
tFE
tAS
ns
8-bit operation mode
4-bit operation mode
RS, R/W address hold time
Data output delay
Data hold time
tAH
tDS
tDHR
-
-
-
ns
ns
ns
Refer to Fig. 3 , the bus timing diagram for read mode .
Table 7
Parameter
Enable cycle time
Enable ”High” level pulse width
Enable rise time
Enable fall time
RS, R/W set-up time
Symbol
tCYCE
tWHE
tRE
Min.
500
300
-
Max.
Unit
ns
ns
ns
ns
Remarks
-
-
25
25
-
tFE
tAS
-
60
100
10
-
ns
8-bit operation mode
4-bit operation mode
RS, R/W address hold time
Read data output delay
Read data hold time
tAH
tRD
tDHR
-
190
-
ns
ns
ns
20