VL-FS-MDLS12433P-01 REV. A
(MDLS12433P-LV-S)
MAR/2004
PAGE 8 OF 10
4.3
Timing Specifications
Ta = 0 °C to +50 °C, VCC =5V±5%, GND=0V; VLCD= VCC-3.5V to VCC-9V.
Refer to Fig.2, I2C Bus Timing Diagram of ’PHILIPS’ PCF2116; rise and fall times referring to VIL and
VIH.
Table 6
Parameters
Symbol Min. Typ. Max. Unit
LCD frame frequency (internal clock) (note 1)
External clock frequency
Timing characteristics: I2C-bus interface; note 2
SCL clock frequency
fFR
40
90
65
100
225
Hz
fOSC
150
kHz
fSCL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
100
kHz
ns
Tolerable spike width on bus
Bus free time
tSW
100
tBUF
4.7
4.7
4
-
-
µs
µs
µs
µs
µs
µs
µs
ns
Set-up time for a repeated START condition
Start condition hold time
SCL LOW time
tSU;STA
tHD;STA
tLOW
tHIGH
tr
-
4.7
4
-
-
250
0
4
-
SCL HIGH time
-
SCL and SDA rise time
SCL and SDA fall time
Data set-up time
1
0.3
-
tf
tSU;DAT
tHD;DAT
tSU;STO
Data hold time
-
-
ns
µs
Set-up time for Stop condition
Notes:
1 VCC=5.0V.
2. All timing values are valid within the operating supply voltage and ambient temperature range and are
referenced to VIL and VIH with an input voltage swing to GND to VCC.
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