VL-FS-COG-VLGT6566-04 REV.B
(COG-VLGT6566-04)
OCT/2010
PAGE 8 OF 18
3. Interface signals
Table 2(a): Pin assignment
Description
Ground.
Pin No.
1~2
Symbol
VSS
VDD
(VDDIO,VCI)
3~4
Power supply.
5
R0
6
R1
7
R2
8
R3
9
R4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
Digital data input.
R7~R0/G7~G0/B7~B0 are used.
B5
B6
B7
VSS
Ground.
PCLK
(CLK/DOTCLK)
30
Clock signal for data latching in RGB interface.
Display on/off mode control. Internally pulled high.
31
PON (DISP) (a) DISP=L, standby mode.
(b) DISP=H, normal display mode.
HSYNC
32
33
Horizontal sync input in RGB interface.
(HS)
VSYNC
Vertical sync input in RGB interface.
(VS)
34
35
DE
NC
Input data enable control in RGB interface.
No connection.