US1050
output voltage of the regulator. As shown in this figure,
the ESR of the output capacitor produces an instanta-
neousdropequaltothe(DVESR=ESR*DI) and the ESL
effect will be equal to the rate of change of the output
current times the inductance of the capacitor. (DVESL
=L*DI/Dt) . The output capacitance effect is a droop in
the output voltage proportional to the time it takes for
the regulator to respond to the change in the current ,
(DVC = Dt * DI / C ) where Dt is the response time of the
regulator.
37
ESR £
=8 mW
4.6
The Sanyo MVGX series is a good choice to achieve
both price and performance goals.The 6MV1500GX ,
1500uF, 6.3V has an ESR of less than 36 mW typ .
Selecting 5 of these capacitors in parallel has an ESR
of »7.2 mW which achieves our design goal.
The next step is to calculate the drop due to the capaci-
tance discharge and make sure that this drop in voltage
is less than the selected ESL drop in the previous step.
VESR
2) The output capacitance is 5X1500 uF = 7500uF
VESL
VC
Dt ´ DI 2´ 4.6
T
DVC =
=
=1.2 mV
C
7500
Where :
LOAD
CURRENT
1050plt1-1.0
Dt=2 uS is the regulator response time
To set the output DC voltage, we need to select R1 and
R2 :
LOAD CURRENT RISE TIME
3) Assuming R1=121 W , 0.1%
Figure 4 - Typical Regulator response to the fast load
current step.
VOUT
3.5
æ
ö
æ
ö
R2=
- 1 ´ 121=
- 1 ´ 121=217.8 W
÷
ç
÷
ç
è
ø
è
ø
VREF
1.25
An example of a regulator design to meet the Intel
P54Cä VRE specification is given below .
Select R2=218 W ,0.1%
Assume the specification for the processor as shown in
Table 1:
Selecting both R1 and R2 resistors to be 0.1% toler-
ance, results in the least amount of error introduced by
the resistor dividers leaving » ±1.3% error budget for
the US1050 reference which is within the initial accu-
racy of the device.
Type of
Processor
Intel-P54C VRE
Vout
Nominal
3.50 V
Imax
Max Allowed
Output Tolerance
±100 mV
4.6 A
Table 1 - Processr Specification
Finally , the input capacitor is selected as follows :
4) Assuming that the input voltage can drop 150mV be-
fore the main power supply responds, and that the main
power supply response time is » 50 uSec, then the mini-
mum input capacitance for a 4.6A load step is given by
The first step is to select the voltage step allowed in the
output due to the output capacitor’s ESR :
1) Assuming the regulator’s initial accuracy plus the re-
sistor divider tolerance is » ±53 mV (±1.5% of 3.5V nomi-
nal) ,then the total step allowed for the ESR and the
ESL, is - 47 mV .
Assuming that the ESL drop is - 10mV ,the remaining
ESR step will be - 37 mV . Therefore the output capaci-
tor ESR must be :
4.6´ 50
CIN =
=1530 mF
0.15
Rev. 1.3
10/27/00
2-38
UNISEM [ UNISEM ]
