20-40GHz Medium Power Amplifier
CHA3093c
Typical Bias Tuning
The circuit schematic is given below :
Vd1
Vd 2,3,4
IN
OUT
Vg1
Vg2
Vg3,4
Vdet
For medium power operation, the four drain biases are connected altogether. In a same way, all the
gate biases are connected together at the same power supply, tuned to drive a small signal
operating current of 300mA. A separate access to the gate voltages of the two first stages ( Vg1,2 )
is provided in order to be able to tune the first stages for the application, as a lower noise amplifier or
a multiplier.
An additional pad is provided for monitoring the output power, using the Build In Test. This access,
when connected to an external resistor of 10 kOhm ( typical value ) provides a DC voltage which
follows the output power level.
On wafer power measurements versus output power
Ref. : DSCHA30932158 -07-June-02
8/10
Specifications subject to change without notice
United Monolithic Semiconductors S.A.S.
Route Départementale 128 - B.P.46 - 91401 Orsay Cedex France
Tel. : +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09
UMS [ UNITED MONOLITHIC SEMICONDUCTORS ]
