e
m
-
-
-
-
-
U M 3 7 5 8
(see Fig.
consecutive long
secutive short
A logic zero is encoded as
a logic one as
General
and an open as a long pulse
The operating mode of the UM3756 series is
followed by a short pulse.
is encoded into logic
is the
the state of data pin is either one or
is one connected to or open and
transmitted data
or one and the data pulse
as the address pulse (see Fig. ie.,
by the MODE pin. When the ‘MODE’ pin is connected to
VDO the circuit will automatically switch to encoder
mode, then
‘RX pin act as an idle pin. When ‘MODE’ pin is
connected to Vss the circuit will switch to decoder
OUT’ pin
as data out pin and
The data
connected to Vss.
mode, then
comparison is
and
OUT” pin will switch to LOW if
otherwise this pin will keep HIGH,
The
samples the 18
tri-state address
receives waveform from detect circuit.
and
this parallel address data for
mitting. These 16 address pins may
three states (0, 1, open) allowing 3
in either of
Mode
possible
address and
then
provides
The encoder mode is selected by connecting “MODE
pin to
3 = 531,441 possible
binations.
The transmit sequence is initiated by the power
nection and continuously transmits till power down.
address bit is encoded into address
The
and
provide address
and data bits, as described in Table 1.
Data
Bits
Data
Combinations
Address
Bits
Address
Combinations
Part
Number
256
16
10
a
59,049
6,561
4
Table 1
Decoder Mode
(ex.
If the address bits
are assumed to be address bi.
the address bits from
The decoder mode is selected by connecting “MODE” pin
to vss.
detect circuit, the next eight data bits are stored
The decoder receives the serial data from the detect
circuit and outputs the comparison result or data, if
it is valid. The received data may
without data and with data.
and
to the last valid data stored. When the
word with data is received, the address bis
again, and if it does, the data bits are
against the previous stored data biis. If
must
the two words (eight bits data
of data
For decoder without data
such as
and
the data is transferred to the output data pins
the address word is examined bit by bit as
D2 to
pins will
switches to HIGH; for
will the data
If the decoder is momentary type, the data
received; if two successive address words
the
OUT” pin will
address
the data till the
OUT’ pin
address bis of
switch to LOW and
words will
the
successive
OUT” pin to return to HIGH
decoder, the data pins
the next valid data appears
(see Fig. 3-2). Although the address bits
(see Fig. 3-l).
open), the data information must be
state (0, 1,
either one or
An open state will be
as
For decoder with data IC, such as
and
a logic one. The above table (Table 1) also describes
these (decoder with data).
___
the address word with data word are
examined bit by bi as received. The first 10 bits
..
UMC [ UMC CORPORATION ]
