PA4867
CMOS IC
PIN CONFIGURATION
PIN DESCRIPTION
PIN NO.
PIN NAME
SHUTDOWN
GND
I/O
I
PIN DESCRIPTION
1
Entire IC into the shutdown mode when this pin connected to the VDD
Ground
2, 7, 19
3
+OUTA
VDD
O
Channel A + output in BTL mode, high impedance in SE mode
Supply voltage
4, 17
5
-OUTA
-INA
O
I
Channel A - output in BTL mode, + output in SE mode
Inverting input of channel A
6
8
+INA
I
Non-inverting input of channel A, connected to BYPASS pin inside the IC
Inverting input of channel A2
9
-INA2
I
10
11
12
13
14
15
16
18
20
MUX CTRL
-INB2
I
I
Inverting input of channel B2
NC
No Connection
+INB
Non-inverting input of channel B, connected to BYPASS pin inside the IC
Internal mid-supply bias reference bypassing
Inverting input of channel B
BYPASS
-INB
I
-OUTB
+OUTB
HP-IN
O
O
I
Channel B - output in BTL mode, + output in SE mode
Channel B + output in BTL mode, high impedance in SE mode
Output mode select, connected to the VDD for SE mode or GND for BTL mode
UNISONIC TECHNOLOGIES CO., LTD
2 of 7
QW-R502-125.A
www.unisonic.com.tw
UMC [ UMC CORPORATION ]
