Transcend 44-Pin IDE Flash Module
TS128M ~ 8GDOM44V-S
True IDE Multiword DMA Mode Read/Write Timing Specification
Mode 0
(ns)
Mode 1
(ns)
Mode 2
(ns)
Mode 3
(ns)
Mode 4
(ns)
Item
Cycle time (min) 1
-IORD / -IOWR asserted width(min) 1
-IORD data access (max)
-IORD data hold (min)
t0
tD
480
215
150
5
150
80
60
5
120
70
50
5
100
65
50
5
80
55
45
5
tE
tF
tG
tH
-IORD/-IOWR data setup (min)
-IOWR data hold (min)
100
20
30
15
0
20
10
0
15
5
10
5
tI
DMACK to –IORD/-IOWR setup (min)
-IORD / -IOWR to -DMACK hold (min)
-IORD negated width (min) 1
-IOWR negated width (min) 1
-IORD to DMARQ delay (max)
-IOWR to DMARQ delay (max)
CS(1:0) valid to –IORD / -IOWR
CS(1:0) hold
0
0
0
tJ
20
5
5
5
5
tKR
tKW
tLR
tLW
tM
tN
50
50
50
40
40
30
10
25
25
25
35
35
25
10
25
25
25
35
35
10
10
25
20
20
35
35
5
215
120
40
50
15
10
25
tZ
-DMACK
20
Notes:
(1) t0 is the minimum total cycle time and tD is the minimum command active time, while tKR and tKW are the
minimum command recovery time or command inactive time for input and output cycles respectively. The
actual cycle time equals the sum of the actual command active time and the actual command inactive time.
The three timing requirements of t0, tD, tKR, and tKW shall be met. The minimum total cycle time requirement
is greater than the sum of tD and tKR or tKW.for input and output cycles respectively. This means a host
implementation can lengthen either or both of tD and either of tKR, and tKW as needed to ensure that t0 is
equal to or greater than the value reported in the device’s identify device data.
8
Transcend Information Inc.
Ver 1.2
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