TS32M~1GCF80
80X CompactFlash Card
3.2 Signal Description
Signal Name
Dir.
Pin
Description
A10 – A00
I
8,10,11,12, These address lines along with the -REG signal are used to select the following:
14,15,16,17, The I/O port address registers within the CompactFlash Storage Card , the
(PC Card Memory Mode)
18,19,20
memory mapped port address registers within the CompactFlash Storage Card,
a byte in the card's information structure and its configuration control and status
registers.
A10 – A00
This signal is the same as the PC Card Memory Mode signal.
(PC Card I/O Mode)
I
A02 - A00
18,19,20
In True IDE Mode, only A[02:00] are used to select the one of eight registers
in the Task File, the remaining address lines should be grounded by the
host.
(True IDE Mode)
BVD1
I/O
46
This signal is asserted high, as BVD1 is not supported.
(PC Card Memory Mode)
-STSCHG
This signal is asserted low to alert the host to changes in the READY and Write
Protect states, while the I/O interface is configured. Its use is controlled by the
Card Config and Status Register.
(PC Card I/O Mode)
Status Changed
-PDIAG
In the True IDE Mode, this input / output is the Pass Diagnostic signal in the
Master / Slave handshake protocol.
(True IDE Mode)
BVD2
I/O
45
This signal is asserted high, as BVD2 is not supported.
(PC Card Memory Mode)
-SPKR
This line is the Binary Audio output from the card. If the Card does not support
the Binary Audio function, this line should be held negated.
(PC Card I/O Mode)
-DASP
In the True IDE Mode, this input/output is the Disk Active/Slave Present signal in
the Master/Slave handshake protocol.
(True IDE Mode)
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