Transcend 40-Pin IDE Flash Module
TS128M ~ 16GDOM40V-S
True IDE PIO Mode Read/Write Timing
Mode Mode Mode Mode Mode Mode Mode
Item
0
600
70
1
383
50
2
240
30
3
180
30
4
120
25
5
100
15
6
80
10
55
55
20
15
5
t0 Cycle time (min) 1
t1 Address Valid to -IORD/-IOWR setup (min)
t2 -IORD/-IOWR (min) 1
165
290
--
125
290
--
100
290
--
80
80
70
30
10
20
5
70
70
25
20
10
20
5
65
65
25
20
5
t2 -IORD/-IOWR (min) Register (8 bit)
t2i -IORD/-IOWR recovery time (min)
t3 -IOWR data setup (min)
60
30
50
5
45
20
35
5
30
15
20
5
t4 -IOWR data hold (min)
t5 -IORD data setup (min)
15
5
10
5
t6 -IORD data hold (min)
t6Z -IORD data tristate (max)2
30
90
60
20
30
50
45
15
30
40
30
10
30
N/A
N/A
10
30
N/A
N/A
10
20
N/A
N/A
10
20
N/A
N/A
10
t7 Address valid to IOCS16 assertion (max) 4
t8 Address valid to IOCS16 released (max) 4
t9 -IORD/-IOWR to address valid hold
tRD Read Data Valid to IORDY active (min), if
IORDY initially low after tA
0
0
0
0
0
0
0
tA IORDY Setup time 3
35
35
35
35
35
N/A5 N/A5
tB IORDY Pulse Width (max)
1250 1250 1250 1250 1250 N/A5 N/A5
tC IORDY assertion to release (max)
5
5
5
5
5
N/A5 N/A5
Notes: All timings are in nanoseconds. The maximum load on -IOCS16 is 1 LSTTL with a 50 pF (40pF below
120nsec Cycle Time) total load. All times are in nanoseconds. Minimum time from -IORDY high to -IORD
high is 0 nsec, but minimum -IORD width shall still be met.
(1) t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum
command recovery time or command inactive time. The actual cycle time equals the sum of the actual
command active time and the actual command inactive time. The three timing requirements of t0, t2, and
t2i shall be met. The minimum total cycle time requirement is greater than the sum of t2 and t2i. This means
a host implementation can lengthen either or both t2 or t2i to ensure that t0 is equal to or greater than the
value reported in the device’s identify device data.
(2) This parameter specifies the time from the negation edge of -IORD to the time that the data bus is
released by the device.
(3) The delay from the activation of -IORD or -IOWR until the state of IORDY is first sampled. If IORDY is
inactive then the host shall wait until IORDY is active before the PIO cycle can be completed. If the device
is not driving IORDY negated at tA after the activation of -IORD or -IOWR, then t5 shall be met and tRD is not
applicable. If the device is driving IORDY negated at the time tA after the activation of -IORD or -IOWR,
then tRD shall be met and t5 is not applicable.
(4) t7 and t8 apply only to modes 0, 1 and 2. For other modes, this signal is not valid.
(5) IORDY is not supported in this mode.
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