TS7003
TIMING SPECIFICATIONS
VDD = +2.7V to +3.6V, TA = -40ºC to +85ºC, unless otherwise noted.
PARAMETER
SCLK Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
SYMBOL
CONDITIONS
MIN
208
83
TYP
MAX
UNITS
ns
ns
tCP
tCH
tCL
83
ns
45
tCSS
ns
CS Fall to SCLK Rise Setup
SCLK Rise to CS Rise Hold
SCLK Rise to CS Fall Ignore
0
tCSH
tCSO
ns
ns
45
45
13
tCS1
tDOH
tDOV
tDOD
ns
ns
ns
ns
CS Rise to SCLK Rise Ignore
SCLK Rise to DOUT Hold
SCLK Rise to DOUT Valid
CLOAD = 20pF
CLOAD = 20pF
CLOAD = 20pF; Refer to Figure 2
100
85
13
CS Rise to DOUT Disable
CS Fall to DOUT Enable
CS Pulse-Width High
tDOE
tCSW
CLOAD = 20pF; Refer to Figure 1
85
ns
ns
100
Note 1: Tested at VDD = VDD(MIN)
.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been
calibrated.
Note 3: Internal reference, offset, and reference errors nulled.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5: External load should not change during conversion for specified accuracy. Guaranteed specification limit of 2mV/mA because of
production test limitations.
Note 6: Electrical characteristics are guaranteed from VDD(MIN) to VDD(MAX). For operations beyond this range, see Typical Operating
Characteristics.
Note 7: TS7003 tested with 20pF on DOUT and fSCLK = 4.8MHz, 0 to 3V. DOUT = full scale.
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TS7003DS r1p0
RTFDS
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