TS7001
TIMING SPECIFICATIONS1
VDD = +2.7V to +3.6V; TA = TMIN to TMAX, unless otherwise noted.
Parameter
Limit
Unit
Description
2
External serial clock
Conversion Time
fSCLK
3
MHz (max)
tCONVERT
tACQ
14.5 × tSCLK
1.5 × tSCLK
Throughput Time = tCONVERT + tACQ = 16 tSCLK
t1
10
ns (min)
ns (max)
ns (max)
ns (min)
ns (min)
ns (min)
ns (min)
ns (max)
μs (typ)
CS to SCLK Setup Time
3
t2
60
Delay from CS until DOUT three-state disabled
Data Access Time after SCLK High-to-Low Edge
3
t3
100
t4
t5
t6
t7
20
Data Setup Time prior to SCLK Low-to-High Edge
Data Valid to SCLK Hold Time
SCLK high Pulse Width
20
0.4 × tSCLK
0.4 × tSCLK
80
SCLK low Pulse Width
4
t8
CS rising edge to DOUT High-Z
Power-up Time from Shutdown
t9
5
Note 1: Timing specifications are sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of
VDD) and timed relative to a voltage level of 1.6V.
Note 2: The mark/space ratio for the SCLK input is 40/60 to 60/40. See Serial Interface section for additional details.
Note 3: Measured with the load circuit as shown below and defined as the time required for the output to cross 0.8V or 2.0V.
Note 4: Timing specification t8 is derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit shown
below. The measured result is then extrapolated back to remove the effects of charging or discharging the 50pF capacitor. This
means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the TS7001 and is independent of bus
loading.
Load Circuit Used for TS7001’s Digital Output Timing
Specifications.
TS7001DS r1p0
Page 5
RTFDS
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