TS3006
ELECTRICAL CHARACTERISTICS
VDD = 3V, VPWM_CNTRL= VDD, RSET = 4.32MΩ, RLOAD(FOUT) = Open Circuit, CLOAD(FOUT) = 0pF unless otherwise noted. Values are at TA = 25°C
unless otherwise noted. See Note 1.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
VDD
1.55
5.25
V
1.9
2.4
2.7
41.2
42
Supply Current
FOUT Period
IDD
µA
µs
-40°C ≤ TA ≤ 85°C
-40°C ≤ TA ≤ 85°C
39
38
40.1
0.17
tFOUT
FOUT Period Line
Regulation
ΔtFOUT/V
1.55V ≤ VDD ≤ 5.25V
%/V
%
FOUT Duty cycle
49
51
FOUT Period
Temperature
Coefficient
ΔtFOUT/ΔT
0.02
%/°C
UVLO Hysteresis
FOUT Rise Time
FOUT Fall Time
FOUT Jitter
VUVLO
tRISE
(VDD=1.55V) – (VDD
_
)
150
250
mV
ns
ns
%
SHUTDOWN VOLTAGE
See Note 2, CL = 15pF
See Note 2, CL = 15pF
See Note 3
10
10
tFALL
0.001
0.3
RSET Pin Voltage
V(RSET)
Fosc
V
Maximum Oscillator
Frequency
High Level Output
Voltage, FOUT
Low Level Output
Voltage, FOUT
RSET= 360K
IOH = 1mA
300
kHz
mV
mV
VDD - VOH
VOL
160
140
IOL = 1mA
Note 1: All devices are 100% production tested at TA = +25°C and are guaranteed by characterization for TA = TMIN to TMAX, as specified.
Note 2: Output rise and fall times are measured between the 10% and 90% of the VDD power-supply voltage levels. The specification is based
on lab bench characterization and is not tested in production.
Note 3: Timing jitter is the ratio of the peak-to-peak variation of the period to the mean of the period. The specification is based on lab bench
characterization and is not tested in production.
TS3006DS r1p0
Page 3
RTDFS