TS3004
With an RSET = 4.32MΩ and FDIV2:0=111, the FOUT
period is approximately 83.89s with a 50% duty cycle.
As design aids, Tables 2 lists TS3004’s typical ꢀOꢁT
period for various standard values for RSET and
FDIV2:0 = 111(7).
Connect CPWM to VDD to disable the PWM function
and in turn, save power. Connect PWM_CNTRL to
VDD for a fixed PWMOUT output pulse width, which
is determined by the CPWM pin capacitor only.
APPLICATIONS INFORMATION
The output period can be user-adjusted from 3.3µs to
233s without additional components. Frequency
divider inputs FDIV2:0 can be set to a logic state
HIGH or LOW in order to set the desired frequency
as shown in to Table 1.
Minimizing Power Consumption
To keep the TS3004’s power consumption low,
resistive loads at the FOUT and PWMOUT terminals
increase dc power consumption and therefore should
be as large as possible. Capacitive loads at the
FOUT and PWMOUT terminals increase the
TS3004’s transient power consumption and, as well,
should be as small as possible.
The TS3004 also provides a separate PWM output
signal at its PWMOUT terminal that is anti-phase with
respect to FOUT. A dead time of approximately
106ns exists between FOUT and PWMOUT. To
adjust the pulse width of the PWMOUT output, a
single capacitor can be placed at the CPWM pin. To
determine the capacitance needed for a desired
pulse width, the following equation is to be used:
One challenge to minimizing the TS3004’s transient
power consumption is the probe capacitance of
oscilloscopes and frequency counter instruments.
Most instruments exhibit an input capacitance of
15pF or more. Unless buffered, the increase in
transient load current can be as much as 400nA.
ꢈulse Widthꢂsꢃ x ꢅCꢈWM
CꢈWMꢂꢀꢃ=
VCꢈWMꢀꢁꢀ300mV
Equation 2. CPWM Capacitor Calculation
where ICPWM and VCPWM is the current supplied and
voltage applied to the CPWM capacitor, respectively.
The pulse width is determined based on the period of
FOUT and should never be greater than the period at
FOUT. Make sure the PWM_CNTRL pin is set to at
least 400mV when calculating the pulse width of
PWMOUT. Note VCPWM is approximately 300mV,
which is the RSET voltage. Also note that ICPWM is
either 1µA or 100nA. Refer to Table 1.
Figure 1: Using an External Capacitor in Series with
Probes Reduces Effective Capacitive Load.
The PWMOUT output pulse width can be adjusted
further after selecting a CPWM capacitor. This can be
achieved by applying a voltage to the PWM_CNTRL
pin between VRSET and GND. With a voltage of at
least VRSET, the pulse width is set based on Equation
2. For example, with a period of 40µs( 25kHz) a 47pF
capacitor at the CPWM pin generates a pulse width
of approximately 16µs. This can be calculated using
equation 2. By reducing the PWM_CNTRL voltage
from VRSET ꢁ 300mV to GND, the pulse width is
reduced from 16µs to approximately 8µs. This is a
pulse width reduction of 50%. Note that as the FOUT
frequency increases, the amount of pulse width
reduction reduces and vice versa. Furthermore, if the
PWMOUT output is half the frequency of the FOUT
output, this means your CPWM capacitor is too large
and as a result, the pulse width is greater than the
FOUT period. In this case, use Equation 2 and
reduce the capacitor value to less than the period.
To minimize capacitive loading, the technique shown
in Figure 1 can be used. In this circuit, the principle of
series-connected capacitors can be used to reduce
the effective capacitive load at the TS3004’s ꢀOꢁT
and PWMOUT terminals.
To determine the optimal value for CEXT once the
probe capacitance is known by simply solving for
CEXT using the following expression:
1
CꢇꢉTꢀ=ꢀ
1
ꢀ1
ꢀꢋꢀ
CꢊOAꢄꢂꢇꢀꢀꢃ CꢈROꢌꢇ
Equation 3:External Capacitor Calculation
Page 8
TS3004DS r1p0
RTFDS
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