Functional Overview
With High Speed CML SerDes, proprietary encoding scheme and CDR (Clock and Data Recovery)
architecture, the THCV231 and THCV236 enable transmission of 14bit data through Main-Link by single
differential pair cable with minimal external components. In addition, the THCV231 and THCV236 have
Sub-Link which enables bi-directional transmission of 2-wire serial interface signals, GPIO signals and also
HTPDN/LOCKN signals for Main-Link through the other 1-pair of CML-Line. It does not need any external
frequency reference such as a crystal oscillator. The THCV231 - THCV236 system is able to watch peripheral
devices and to control them via 2-wire serial interface or GPIOs. They also can report interrupt events caused by
change of GPIO inputs and internal statuses.
Functional Description
Internal Reference Output/Input Function (CAPOUT, CAPINA, CAPINP)
An internal regulator produces the 1.2V (CAPOUT). This 1.2V linear regulator can’t supply any other
external loads. Bypass CAPOUT to GND with 10uF.
CAPINP (THCV231 only) supplies reference voltage for internal PLL, and CAPINA supplies reference
voltage for any internal analog circuit. Bypass CAPINP/CAPINA to GND with 0.1uF to remove high frequency
noise. CAPOUT, CAPINA and CAPINP must be tied together.
Power supply AVDD is supposed to be stabilized with de-coupling capacitor and series noise filter (for example,
ferrite bead).
THCV236
THCV231
10uF
10uF
0.1uF
0.1uF
Power
Supply
Power
Supply
AVDD
CAPOUT
AVDD
CAPOUT
0.1uF
CAPINA
CAPINA
CAPINP
Figure 1. Connection of CAPOUT, CAPINA, CAPINP and Decoupling Capacitor
THCV231_THCV236_Rev.2.30_E
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