THine
THC63LVD104A Rev.1.0
Pin Description
Pin Name
RA+, RA-
RB+, RB-
Pin #
50, 49
Type
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
OUT
Description
52, 51
RC+, RC-
55, 54
LVDS Data In.
LVDS Clock In.
RD+, RD-
RE+,RE-
60, 59
62, 61
RCLK+, RCLK-
RA6 ~ RA0
RB6 ~ RB0
RC6 ~ RC0
RD6 ~ RD0
RE6 ~ RE0
TEST
57, 56
40,41,42,43,45,46,47
32,33,34,35,36,38,39
22,24,25,26,27,28,29
14,15,17,18,19,20,21
6,7,8,10,11,12,13
2
OUT
OUT
CMOS/TTL Data Outputs.
OUT
OUT
IN
Test pin, must be “L” for normal operation.
H: Normal operation,
PD
OE
R/F
3
4
5
IN
IN
IN
L: Power down (all outputs are “L”)
H:Output enable (Normal operation).
L:Output disable(all outputs are Hi-Z)
Output Clock Triggering Edge Select.
H: Rising edge, L: Falling edge
Power Supply Pins for TTL outputs and digital
circuitry.
VCC
CLKOUT
GND
9,23,37,48
31
Power
OUT
Clock out.
Ground Pins for TTL outputs and digital cir-
cuitry.
1,16,30,44
Ground
LVCC
LGND
PVCC
PGND
53
58
64
63
Power
Ground
Power
Power Supply Pin for LVDS inputs.
Ground Pin for LVDS inputs.
Power Supply Pin for PLL circuitry.
Ground Pin for PLL circuitry.
Ground
Data Outputs
PD
R/F
OE
CLKOUT
(Rxn)
Hi-Z
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Hi-Z
All 0
Fixed Low
Hi-Z
Hi-Z
All 0
Fixed Low
Hi-Z
Hi-Z
Data Out
Hi-Z
It latches output data on falling edge.
Hi-Z
Data Out
It latches output data on rising edge.
** Rxn
x = A,B,C,D,E
n = 0,1,2,3,4,5,6
Copyright 2003 THine Electronics, Inc. All rights reserved
3
THine Electronics, Inc.
THINE [ THINE ELECTRONICS, INC. ]
