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THC63LVD824A 参数 Datasheet PDF下载

THC63LVD824A图片预览
型号: THC63LVD824A
PDF下载: 下载PDF文件 查看货源
内容描述: [Single(112MHz)/Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA/UXGA]
分类和应用:
文件页数/大小: 14 页 / 148 K
品牌: THINE [ THINE ELECTRONICS, INC. ]
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THC63LVD824A _Rev1.20_E  
Supply Current  
V
= 3.0V ~ 3.6V, Ta = -10°C ~ +70°C  
CC  
Symbol  
Parameter  
Condition(*)  
Typ. Max. Units  
Receiver Supply  
Current  
MODE<1:0>=LL  
I
f
= 85MHz  
CLKOUT  
225  
10  
mA  
RCCW  
CL=8pF,  
Vcc=3.6V  
(Worst Case Pattern)  
Receiver Power Down  
Supply Current  
I
/PDWN = L  
μA  
RCCS  
Switching Characteristics  
V
= 3.0V ~ 3.6V, Ta = -10°C ~ +70°C  
CC  
Symbol  
Parameter  
Min.  
11.76  
Typ.  
Max.  
Units  
ns  
t
Dual-in / Dual-out  
Single-in / Dual-out  
40.0  
80.0  
RCIP  
t
CLKOUT Period  
RCP  
2t  
17.85  
ns  
RCIP  
tRCP  
----------  
2
t
CLKOUT High Time  
CKLOUT Low Time  
ns  
ns  
RCH  
tRCP  
----------  
2
t
RCL  
t
0.3t  
0.3t  
-0.5  
TTL Data Setup to CLKOUT  
ns  
ns  
ns  
RS  
RCP  
t
-0.5  
RCP  
TTL Data Hold from CKLOUT  
TTL Low to High Transition Time  
TTL High to Low Transition Time  
RH  
t
2.5  
4.0  
4.0  
TLH  
t
2.5  
ns  
ns  
ns  
ns  
THL  
CLKIN=85MHz  
CLKIN=112MHz  
-0.40  
-0.25  
+0.40  
+0.25  
Receiver Skew  
Margin  
t
SK  
t
t
-t  
+t  
Input Data Position0  
Input Data Position1  
0.0  
RIP1  
RIP0  
SK  
SK  
tRCIP  
tRCIP  
------------  
7
tRCIP  
ns  
ns  
ns  
ns  
ns  
ns  
------------ – tSK  
7
------------ + tSK  
7
tRCIP  
tRCIP  
2------------  
7
tRCIP  
t
t
t
t
t
Input Data Position2  
Input Data Position3  
Input Data Position4  
Input Data Position5  
Input Data Position6  
2------------ – tSK  
7
2------------ + tSK  
7
RIP6  
RIP5  
RIP4  
RIP3  
RIP2  
tRCIP  
tRCIP  
3------------  
7
tRCIP  
3------------ – tSK  
7
3------------ + tSK  
7
tRCIP  
tRCIP  
4------------  
7
tRCIP  
4------------ – tSK  
7
4------------ + tSK  
7
tRCIP  
tRCIP  
5------------  
7
tRCIP  
5------------ – tSK  
7
5------------ + tSK  
7
tRCIP  
tRCIP  
6------------  
7
tRCIP  
6------------ – tSK  
7
6------------ + tSK  
7
t
Phase Lock Loop Set  
CLKIN Period  
10.0  
40.0  
ms  
ns  
RPLL  
t
8.92  
RCIP  
Skew Time between RCLK1 and  
RCLK2  
t
ns  
CK12  
±0.3tRCIP  
Copyright©2014 THine Electronics, Inc.  
5/14  
THine Electronics, Inc.