THC63LVD104S Rev.1.0
AC Timing Diagrams
TTL Output
80%
80%
C =8pF
L
20%
20%
TTL Output Load
t
t
THL
TLH
Fig3. CMOS/TTL Output Load and Transition Time
t
RCP
t
t
RCL
RCH
V
/2
CLKOUT
V
/2
V
/2
CC
V
2
CC/
CC
CC
Fig4. CLKOUT Period and High/Low Time
t
RCP
R/F=L
R/F=H
V
/2
CLKOUT
DK=L
CC
t
t
RS
RH
R/F=H
R/F=L
CLKOUT
DK=M
V
t
/2
CC
RCP
3-------------
14
R/F=L
R/F=H
CLKOUT
DK=H
V
/2
CC
t
RCP
14
3-------------
Rxn
V
/2
V
/2
CC
CC
x = A,B,C,D,E
n = 0~6
Fig5. CLKOUT Position and Setup/Hold Timing
Copyright 2004 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.