THine
THC63LVD104C_Rev.2.1_E
Pin Description
Pin Name
RA+, RA-
Pin #
50, 49
Type
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
OUT
Description
RB+, RB-
52, 51
RC+, RC-
RD+, RD-
RE+,RE-
55, 54
LVDS Data In.
LVDS Clock In.
60, 59
62, 61
RCLK+, RCLK-
RA6 ~ RA0
RB6 ~ RB0
RC6 ~ RC0
RD6 ~ RD0
RE6 ~ RE0
TEST
57, 56
40,41,42,43,45,46,47
32,33,34,35,36,38,39
22,24,25,26,27,28,29
14,15,17,18,19,20,21
6,7,8,10,11,12,13
2
OUT
OUT
CMOS/TTL Data Outputs.
OUT
OUT
IN
Test pin, must be “L” for normal operation.
H: Normal operation,
PD
OE
R/F
3
4
5
IN
IN
IN
L: Power down (all outputs are “L”)
H: Output enable (Normal operation).
L: Output disable(all outputs are Hi-Z)
Output Clock Triggering Edge Select.
H: Rising edge, L: Falling edge
VCC
CLKOUT
GND
9,23,37,48
Power
OUT
Power Supply Pins for TTL outputs and digital circuitry.
Clock out.
31
1,16,30,44
Ground
Power
Ground
Power
Ground
Ground Pins for TTL outputs and digital circuitry.
Power Supply Pin for LVDS inputs.
Ground Pin for LVDS inputs.
LVCC
53
58
64
63
LGND
PVCC
PGND
Power Supply Pin for PLL circuitry.
Ground Pin for PLL circuitry.
Data Outputs
(Rxn)
PD
R/F
OE
CLKOUT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Hi-Z
Hi-Z
All 0
Fixed Low
Hi-Z
Hi-Z
All 0
Fixed Low
Hi-Z
Hi-Z
Data Out
Hi-Z
The falling edge closer to the center of the data eye.
Hi-Z
Data Out
The rising edge closer to the center of the data eye.
** Rxn
x = A,B,C,D,E
n = 0,1,2,3,4,5,6
Copyright©2010 THine Electronics, Inc.
3/13
THine Electronics, Inc.
THINE [ THINE ELECTRONICS, INC. ]
