78Q8392L/A03
Low Power Ethernet
Coaxial Transceiver
JABBER FUNCTION
HEARTBEAT FUNCTION
When valid data on the TX± pins is detected, the
jabber timer is started. If there is valid data for more
than 20 ms, a latch is set which disables the
transmitter output and enables the 10 MHz output on
the CD± pins. The latch is reset within 0.5 seconds
after the valid data is removed from the transmitter
input (TX±). This action resets the jabber timer and
disables the 10 MHz signal on the CD± pins. The
TX± inputs must remain inactive during the 0.5
second reset period.
The 10 MHz CD outputs are enabled for about 1 µs
at approximately 1.1 µs after the end of each
transmission. The heartbeat signal tells the DTE that
the circuit is functioning. This is implemented by
starting the heartbeat timer when the valid data
signal indicates the end of a transmission. This
function is disabled when HBE pin is tied to VEE.
DATA MEDIA
RECEIVER
RXI
INPUT
SLICER
BUFFER
RX+
RX-
EQUALIZER
CDS
RX DATA
VALID
NARROW
PULSE
FILTER
TRANSITION
ENABLE
PERIOD
TAMER
SQUELCH
COMPARATOR
LP FILTER
SQUELSH
THRESHOLD
COLLISION
COMPARATOR
COLLISION
THRESHOLD
TRANSMIT
OUTPUT DRIVER
TRANSMIT INPUT
BUFFER
TXO
BUFFERED TX
TX+
PULSE
SHAPING
FILTER
SLICER
TX-
TX DISABLE
CONTROL LOGIC
JABBER TIMER
TX ON
TX DATA VALID TRANSITION
NARROW
PULSE
FILTER
TX ± > -250 mV
TX ± < -250 mV
PERIOD
TIMER
BLANKING TIMER
COMPARATOR
END TRANSMIT TRANSITION
END
HEART BEAT TIMER
TIMER
TX± DISABLE
SIGNAL
PRESET
DETECT
10 MHz
OSC
ENABLE
CD ± ON
CD+
CD-
BANDGAP
REFERENCE
AND CURRENT
REFERENCE
RR+
RR-
FIGURE 1: 78Q8392L/A03 General System Block Diagram
Page: 3 of 14
© 2008 Teridian Semiconductor Corporation
Rev 1.3
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
