78Q2123/78Q2133 MicroPHY™
10/100BASE-TX Transceiver
When the PHYAD field is all zeros, the Station
Management Entity (STA) is requesting a broadcast
MEDIA INDEPENDENT INTERFACE
MII Transmit and Receive Operation
The MII interface on the 78Q2123/78Q2133 provide
independent transmit and receive paths for both
10Mb/s and 100Mb/s data rates as described in
Clause 22 of the IEEE-802.3 standard.
data transaction.
All PHYs sharing the same
Management Interface must respond to this
broadcast request.
The 78Q2123/78Q2133 will
respond to the broadcast data transaction.
ADDITIONAL FEATURES
The transmit clock, TX_CLK, provides the timing
LED Indicators
reference for the transfer of TX_EN, TXD3-0, and
TX_ER
signals
from
the
MAC
to
the
There are two LED pins that can be used to indicate
78Q2123/78Q2133. TXD3-0 is captured on the
rising edge of TX_CLK when TX_EN is asserted.
TX_ER is also captured on the rising edge of
TX_CLK and is asserted by the MAC to request that
an error code group is to be transmitted. The
assertion of TX_ER is ignored when the
78Q2123/78Q2133 are operating in 10BASE-T
mode.
various
states
of
operation
of
the
78Q2123/78Q2133. The function of these pins is
programmable via the MR23 register as shown in
the table below:
LED STATE INDICATION
0
1
2
3
4
5
6
7
8
1 = Link OK (Default LED0)
1 = RX or TX Activity (Default LED1)
1 = TX Activity
The receive clock, RX_CLK, provides the timing
reference to transfer RX_DV, RXD3-0, and RX_ER
signals from the 78Q2123/78Q2133 to the MAC.
RX_DV transitions synchronously with respect to
RX_CLK
and
is
asserted
when
the
1 = RX Activity
78Q2123/78Q2133 are presenting valid data on
RXD3-0. RX_ER is asserted and is synchronous to
RX_CLK when a code group violation has been
detected in the current receive packet.
1 = Collision
1 = 100 BASE-TX mode
1 = 10 BASE-T mode
1 = Full Duplex
Station Management Interface
The station management interface consists of
circuitry which implements the serial protocol as
described in Clause 22.2.4.4 of IEEE-802.3. A 16-
bit shift register receives serial data applied to the
MDIO pin at the rising-edge of the MDC clock signal.
Once the preamble is received, the station
management control logic looks for the start-of-
frame sequence and a read or write op-code,
followed by the PHYAD and REGAD fields. The
default address for the 78Q2123/78Q2133 is 1. For
a read operation, the MDIO port becomes enabled
as an output and the register data is loaded into a
1= Link OK & Blink = RX or TX Activity
The default status of these LEDs are “Link OK” for
LED0 and “RX or TX Activity” for LED1.
Interrupt Pin
The 78Q2123/78Q2133 have an Interrupt pin (INTR)
that is asserted whenever any of the eight interrupt
bits of MR17.7:0 are set. These interrupt bits can be
disabled via the MR17.15:8 Interrupt Enable bits.
The Interrupt Polarity bit, MR16.14, controls the
active level of the INTR pin. When the INTR pin is
not asserted, the pin is held in a high impedance
state. An external pull-up or pull-down resistor may
be required for use with the INTR pin.
shift
register
for
transmission.
The
78Q2123/78Q2133 can work with
a
one-bit
preamble rather than the 32 bits prescribed by IEEE-
802.3. This allows for faster programming of the
registers. If a register does not exist at an address
indicated by the REGAD field or if the PHYAD field
does not match the 78Q2123/78Q2133 PHYAD, a
read of the MDIO port will return all ones. For a
write operation, the data is shifted in and loaded into
the appropriate register after the sixteenth data bit
has been received.
Writes to registers not
supported by the 78Q2123/78Q2133 are ignored.
Page: 5 of 42
© 2009 Teridian Semiconductor Corporation
Rev 1.5
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