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78Q2120C09-64CGT/F 参数 Datasheet PDF下载

78Q2120C09-64CGT/F图片预览
型号: 78Q2120C09-64CGT/F
PDF下载: 下载PDF文件 查看货源
内容描述: 10 / 100BASE -TX收发器 [10/100BASE-TX Transceiver]
分类和应用: 网络接口电信集成电路电信电路编码器局域网(LAN)标准
文件页数/大小: 35 页 / 589 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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78Q2120C  
10/100BASE-TX  
Transceiver  
Station Management Interface  
78Q2120C. There is an LED pin that indicates the  
link is up (LEDL), others that indicate the 78Q2120C  
is either transmitting (LEDTX) or receiving (LEDRX),  
one that signals a collision event (LEDCOL), two  
more that reflect the data rate (LEDBTXand LEDBT),  
and one that reflects full duplex mode of operation  
(LEDFDX).  
The station management interface consists of  
circuitry which implements the serial protocol as  
described in Clause 22.2.4.5 of IEEE-802.3. A 16-  
bit shift register receives serial data applied to the  
MDIO pin at the rising-edge of the MDC clock signal.  
Once the preamble is received, the station  
management control logic looks for the start-of-  
frame sequence and a read or write op-code,  
followed by the PHYAD and REGAD fields. For a  
read operation, the MDIO port becomes enabled as  
an output and the register data is loaded into a shift  
register for transmission. The 78Q2120C can work  
with a one bit preamble rather than the 32 bits  
prescribed by IEEE-802.3. This allows for faster  
programming of the registers. If a register does not  
exist at an address indicated by the REGAD field or  
if the PHYAD field does not match the 78Q2120C  
PHYAD indicated by the PHYAD pins, a read of the  
MDIO port will return all ones. For a write operation,  
the data is shifted in and loaded into the appropriate  
register after the sixteenth data bit has been  
received.  
Interrupt Pin  
The 78Q2120C has an Interrupt pin (INTR) that is  
asserted whenever any of the eight interrupt bits of  
MR17.7:0 are set. These interrupt bits can be  
disabled via the MR17.15:8 Interrupt Enable bits.  
The Interrupt Polarity bit, MR16.14, controls the  
active level of the INTR pin. When the INTR pin is  
not asserted, this pin is held in a high impedance  
state. An external pull-up or pull-down resistor may  
be required for use with the INTR pin.  
APPLICATIONS REQUIREMENTS  
RXIP/N Termination Connection  
The input circuitry of the TERIDIAN 78Q2120C has  
changed for continuing performance improvements.  
Device revision C09 requires that the RXIP/N  
termination resistors and transformer center tap  
connections be directly connected to VCC for proper  
When the PHYAD field is all zeros, the Station  
Management Entity (STA) is requesting a broadcast  
data transaction.  
All PHYs sharing the same  
Management Interface must respond to this  
broadcast request. The 78Q2120C will respond to  
the broadcast data transaction.  
receiver operation.  
Refer to Figure 1: Typical  
Applications Circuit for the schematic showing the  
required RXIP/N termination resistors and  
transformer center tap connections to VCC for  
revision 78Q2120C.  
ADDITIONAL FEATURES  
LED Indicators  
There are seven LED pins that can be used to  
indicate various states of operation of the  
Page: 5 of 35  
© 2009 Teridian Semiconductor Corporation  
Rev 1.3