78Q2120C
10/100BASE-TX
Transceiver
MII (continued)
NAME
PIN
TYPE DESCRIPTION
25
COZ RECEIVE ERROR: RX_ER is asserted high when an error is detected during a
frame reception. In PCS bypass mode, this pin becomes the MSB of the receive
5-bit code group. This pin is tristated in the isolate mode.
RX_ER
MDC
18
17
CIS
MANAGEMENT DATA CLOCK: MDC is the clock used for transferring data
via the MDIO pin.
MDIO
CIO MANAGEMENT DATA INPUT/OUTPUT: MDIO is a bi-directional port used to
access management registers within the 78Q2120C. This pin requires an
external pull-up resistor as specified in IEEE-802.3.
PHY ADDRESS
NAME
PIN
TYPE DESCRIPTION
PHYAD[4:0] 12-16
CI
PHY ADDRESS: Allows 31 configurable PHY addresses. The 78Q2120C
always responds to broadcast data transactions via the MII interface when the
PHYAD bits are all zero, independent of the logic levels of the PHYAD pins.
PMA (PHYSICAL MEDIA ATTACHMENT) INTERFACE
NAME
PCSBP
PIN
64
TYPE DESCRIPTION
CID
PCS BYPASS: When high, the 100BASE-TX PCS is bypassed, as well as
the scrambler and descrambler functions. Scrambled 5-bit code groups for
transmission are applied to the TX_ER, TXD[3:0] pins and received on the
RX_ER, RXD[3:0] pins. The RX_DV and TX_EN signals are not valid in this
mode. PCS bypass mode is only valid when 100BASE-TX is enabled and
auto-negotiation is disabled. This mode can also be entered by setting
MR16.1.
CONTROL AND STATUS
NAME
RST
PIN
6
TYPE DESCRIPTION
CIU
ACTIVE-LOW RESET: When pulled low, the pin resets the chip. The reset
pulse must be long enough to guarantee stabilization of the supply voltage
and startup of the oscillator. Refer to the Electrical Specifications for the
reset pulse requirements. There are 2 other ways to reset the chip:
i)
through the internal power-on-reset (activated when the chip is
being powered up)
ii)
through the MII register bit (MR0.15)
PWRDN
7
CID
POWER-DOWN: The 78Q2120C may be placed in a low power consumption
state by setting this signal to logic high. While in the power-down state, the
78Q2120C still responds to management transactions. This power-down
state can also be activated using the PWRDN bit in the MII register (MR0.11).
Page: 7 of 35
© 2009 Teridian Semiconductor Corporation
Rev 1.3
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
