78P2351R
Serial 155M
NRZ to CMI Converter
REGISTER DESCRIPTION (continued)
LEGEND
TYPE DESCRIPTION
TYPE DESCRIPTION
R/O
Read only
R/W Read or Write
R/C
Read and Clear
GLOBAL REGISTERS
ADDRESS 0-0: MASTER CONTROL REGISTER
DFLT
BIT
NAME
TYPE
DESCRIPTION
VALUE
7:5
--
R/W
0X0
Reserved.
Reference Clock Frequency Select:
Selects the reference clock frequency input at CKREFP/N pins.
11: 155.52 MHz (differential LVPECL input)
CKSL
[1:0]
4:3
R/W
X
10: 77.76 MHz (single-ended CMOS input) – Tie CKREFN to ground.
00: 19.44 MHz (single-ended CMOS input) – Tie CKREFN to ground.
Note: Default values depend on the CKSL pin setting upon reset or
power up.
2:1
0
--
R/W
R/W
X0
0
Reserved.
Register Soft-Reset:
When this bit is set, all registers are reset to their default values. This
register bit is self-clearing.
SRST
ADDRESS 0-1: RESERVED
DFLT
VALUE
BIT
NAME
TYPE
DESCRIPTION
7:0
--
R/W
00100X11
Reserved.
ADDRESS 0-2: RESERVED
DFLT
BIT
NAME TYPE
-- R/W
DESCRIPTION
VALUE
7:0
XXXXXXX0 Reserved.
Page: 9 of 31
2006 Teridian Semiconductor Corporation
Rev. 2.1
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
