78P2351R
Serial 155M
NRZ to CMI Converter
SERIAL CONTROL INTERFACE
INTERNAL POWER-ON RESET
The serial port controlled register allows a generic
controller to interface with the 78P2351R. It is used
for mode settings, diagnostics and test, retrieval of
status and performance information, and for on-chip
fuse trimming during production test. The SPSL pin
must be high in order to use the serial port.
Power-On Reset (POR) function is provided on chip.
Roughly 50 µs after Vcc reaches 2.4V at power up,
a reset pulse is internally generated. This resets all
registers to their default values as well as all state
machines within the transceiver to known initial
values. The reset signal is also brought out to the
PORB pin. The PORB pin is a special function
analog pin that allows for the following:
The serial interface consists of 4 pins:
ꢀ
ꢀ
ꢀ
ꢀ
Serial Port Enable (SEN),
Serial Clock (SCK_MON),
Serial Data In (SDI),
•
•
•
Override the internal POR signal by driving in
an external active low reset signal;
Serial Data Out (SDO).
Use the internally generated POR signal to
trigger other resets;
Add external capacitor to slow down the
release of power-on reset (approximately 8µs
per nF added).
The SEN pin initiates the read and write operations.
It can also be used to select a particular device
allowing SCK_MON, SDI and SDO to be bussed
together.
NOTE: Do not pull-up the PORB pin to Vcc or drive
this pin high during power-up. This will prevent the
internal reset generator from resetting the entire chip
and may result in errors.
SCK_MON is the clock input that times the data on
SDI and SDO. Data on SDI is latched in on the
rising-edge of SCK_MON, and data on SDO is
clocked out using the falling edge of SCK_MON.
SDI is used to insert mode, address, and register
data into the chip. Address and Data information
are input least significant bit (LSB) first. The mode
and address bit assignment and register table are
shown in the following section.
SDO is a tristate capable output. It is used to output
register data during a read operation. SDO output is
normally high impedance, and is enabled only during
the duration when register data is being clocked out.
Read data is clocked out least significant bit (LSB)
first.
If SDI coming out of the micro-controller chip is also
tristate capable, SDI and SDO can be connected
together to simplify connections.
The maximum clock frequency for register access is
20MHz.
Page: 7 of 31
2006 Teridian Semiconductor Corporation
Rev. 2.1
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
