78P2351
Single Channel
OC-3/ STM1-E/ E4 LIU
SERIAL CONTROL INTERFACE
PROGRAMMABLE INTERRUPTS
The serial port controlled register allows a generic
controller to interface with the 78P2351. It is used
for mode settings, diagnostics and test, retrieval of
status and performance information, and for on-chip
fuse trimming during production test. The SPSL pin
must be high in order to use the serial port.
In addition to the receiver LOS and LOL status pins,
the 78P2351 provides a programmable interrupt for
the transmitter. In HW control mode, the default
functions of the Tx interrupt is a transmit Loss of
Lock (TXLOL) or FIFO error (FERR).
The serial interface consists of four pins: Serial Port
Enable (SEN_CMI), Serial Clock (SCK_MON), Serial
Data In (SDI_PAR), and Serial Data Out (SDO_E4).
The SEN_CMI pin initiates the read and write
operations. It can also be used to select a
particular device allowing SCK_MON, SDI_PAR
and SDO_E4 to be bussed together.
SCK_MON is the clock input that times the data
on SDI_PAR and SDO_E4. Data on SDI_PAR
is latched in on the rising-edge of SCK_MON,
and data on SDO_E4 is clocked out using the
falling edge of SCK_MON.
SDI_PAR is used to insert mode, address, and
register data into the chip. Address and Data
information are input least significant bit (LSB)
first. The mode and address bit assignment and
register table are shown in the following section.
SDO_E4 is a tri-state capable output. It is used
to output register data during a read operation.
SDO_E4 output is normally high impedance,
and is enabled only during the duration when
register data is being clocked out. Read data is
clocked out least significant bit (LSB) first.
If SDI_PAR coming out of the micro-controller chip is
also tri-state capable, SDI_PAR and SDO_E4 can
be connected together to simplify connections.
Page: 9 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
