78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit
REGISTER DESCRIPTION
REGISTER ADDRESSING
Address Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Sub-Address
SA[1]
Bit 1
Bit 0
Read/
Write
Port Address
Assignment
PA[3]
PA[2]
PA[1]
PA[0]
SA[2]
SA[0]
R/W*
REGISTER TABLE
a) PA[3:0] = 0 : Global Registers
Sub
Reg.
Description
Master Control
Interrupt Control
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr
Name
MSCR
E4
<0>
INPOL
<0>
--
--
<0>
--
<0>
--
<X>
PAR
<0>
--
<1>
--
<X>
CKSL[1] CKSL[0]
--
<X>
--
<X>
--
<X>
--
<X>
MTLOL
<1>
--
SRST
<0>
MFERR
<1>
--
<0>
0
1
2
(R/W)
<X>
--
<X>
--
INTC
(R/W)
--
<0>
--
<0>
--
(R/W)
<X>
<X>
<X>
<X>
b) PA[3:0] = 1, 2 : Port-Specific Registers
Reg.
Name
Sub
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr
0
1
2
3
4
5
MDCR Mode Control
PDTX
<0>
--
PDRX
<0>
--
PMODE SMOD[1] SMOD[0]
MON
<0>
RCLKP
<0>
--
<0>
BST[1]
<0>
--
--
<0>
TCLKP
<0>
TPK
<0>
BST[0]
<0>
--
<0>
--
(R/W)
<X>
LOLOR
<0>
--
<X>
RLBK
<0>
--
<X>
LLBK
<0>
--
<1>
SGCR Signal Control
(R/W)
FRST
<0>
<0>
--
<0>
--
ACR1 Advanced Tx
TXEQ
Control 1
<0>
(R/W)
ACR0
(R/W)
<0>
--
<0>
--
<0>
--
<0>
--
<0>
--
Advanced Tx
--
Control 0
<1>
CMI
<1>
--
<0>
--
<1>
--
<X>
--
<0>
--
<1>
--
<0>
--
MCR2
Mode Control 2
(R/W)
<X>
--
<0>
RXLOS
<X>
<0>
RXLOL
<X>
<0>
--
<X>
<0>
STAT Status Monitor
(R/C)
TXLOL
<X>
FERR
<X>
<X>
<X>
<X>
6-7
--
Reserved
--
--
--
--
--
--
--
--
8
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
