78P2351R 155Mbps NRZ to CMI Converter
Plesiochronous Mode
Clock Synthesizer
Plesiochronous mode represents
a
common
The transmit clock synthesizer is a low-jitter PLL that
generates a 311.04 MHz clock for the CMI encoder.
A synthesized 155.52 MHz reference clock is also
used in both the receive and transmit sides for clock
and data recovery.
condition where the transmit data is not source
synchronous to the reference clock input (i.e. local
crystal oscillator, external loopback). In this mode,
the 78P2351R will recover the clock from the serial
plesiochronous NRZ transmit data and bypass the
internal FIFO.
Pulse Amplitude Adjustment
Controls for adjusting the transmit pulse amplitude
are provided in both hardware and software modes.
Amplitude boosts of 5% and 10% can be enabled by
the TXOUT0 pin or BST[1:0] register bits as follows:
System
Clock
XO
CKREFP
NRZ
NRZ
CMI
CMI
Coax
Coax
CMIP/N
RXP/N
XFMR
XFMR
SIDP/N
BST[1:0] bits
Amplitude
TXOUT0 pin
Framer/
Mapper
TDK
78P2351R
Low
Float
High
0 0
0 1
1 1
Normal
5% boost
10% boost
SODP/N
Figure 1: Plesiochronous Mode
Synchronous Mode
Transmit Backplane Equalizer
An optional fixed equalizer is integrated in the
transmit path for architectures that use LIUs on
active interface cards. The fixed equalizer can
compensate for up to 1.5m of trace and can be
enabled by the TXOUT1 pin or TXEQ bit as follows:
When the NRZ transmit data is source synchronous
with the reference clock applied at CKREFP/N as
shown in Figure 2, the 78P2351R can be optionally
used in synchronous mode or re-timing mode. In
this mode, the 78P2351R will recover the clock from
the serial NRZ data input and pass the data through
an integrated FIFO.
TXEQ bit
Tx Equalizer
TXOUT1 pin
Low
Float
1
0
Enabled
Disabled
System Reference Clock
POWER-DOWN FUNCTION
CKREFP/N
NRZ
NRZ
CMI
CMI
Coax
Coax
CMIP/N
RXP/N
XFMR
XFMR
SIDP/N
Power-down control is provided to allow the
78P2351R to be shut off. Transmit and receive
power-down can be set independently through SW
Framer/
Mapper
TDK
78P2351R
SODP/N
control.
Global power-down is achieved by
powering down both the transmitter and receiver.
Note: the serial interface and configuration
Figure 2: Synchronous
registers are not affected by power-down.
Since the reference clock and transmit clock/data go
through different delay paths, it is inevitable that the
phase relationship between the two clocks can vary
in a bounded manner due to the fact that the
absolute delays in the two paths can vary over time.
The FIFO allows long-term clock phase drift, not
exceeding +/- 25.6ns, to be handled without transmit
error. If the clock wander exceeds the specified
limits, the FIFO will over or under flow, and the
FERR register signal will be asserted. The FIFO is
re-centered by asserting the FRST bit. Note that the
FIFO is also automatically re-centered when the
TXLOL register bit (Transmit Loss of Lock)
transitions from high to low.
The transmitter can also be powered down using the
TXPD control pin. The CMI outputs are tri-stated
during transmit power-down for redundancy
applications.
The TXPD pin is active in both
hardware and software modes.
Note: External remote loopbacks (i.e. loopback
within framer) are not possible in synchronous
operation (FIFO enabled) unless the reference
clock is synchronous with the recovered receive
clock (loop-timing).
5
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
