DS_6613_018
78M6613 Data Sheet
1.4.2 Timers and Counters
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be
configured for counter or timer operations.
In timer mode, the register is incremented every machine cycle, meaning that it counts up after every 12
periods of the MPU clock signal.
In counter mode, the register is incremented when the falling edge is observed at the corresponding
input signal T0 or T1 (T0 and T1 are the timer gating inputs derived from certain DIO pins, see the DIO
Ports section). Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count
rate is 1/2 of the oscillator frequency. There are no restrictions on the duty cycle, however to ensure
proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle.
1.5 On-Chip Resources
1.5.1 Oscillator
The 78M6613 oscillator drives a standard 32.768 kHz watch crystal. These crystals are accurate and do
not require a high-current oscillator circuit. The 78M6613 oscillator has been designed specifically to
handle these crystals and is compatible with their high impedance and limited power handling capability.
1.5.2 PLL and Internal Clocks
Timing for the device is derived from the 32.768 kHz oscillator output. On-chip timing functions include
the MPU master clock and the delta-sigma sample clock. In addition, the MPU has two general
counter/timers.
The ADC master clock, CKADC, is generated by an on-chip PLL. It multiplies the oscillator output
frequency (CK32) by 150.
The CE clock frequency is always CK32 * 150, or 4.9152 MHz, where CK32 is the 32 kHz clock. The
MPU clock frequency is scalable from 4.9152 MHz down to 38.4 kHz. The circuit can also generate a 2x
MPU clock for use by the emulator.
1.5.3 Temperature Sensor
The device includes an on-chip temperature sensor for determining the temperature of the bandgap
reference. The primary use of the temperature data is to determine the magnitude of compensation required
to offset the thermal drift in the system (see Section 3.3 Temperature Compensation).
1.5.4 Flash Memory
The 78M6613 includes 32 KB of on-chip Flash memory. The Flash memory primarily contains MPU and
CE program code. It also contains images of the CE DRAM, MPU RAM, and I/O RAM. On power-up,
before enabling the CE, the MPU copies these images to their respective locations. Allocated Flash
space for the CE program cannot exceed 1024 words (2 KB).
MPU RAM: The 78M6613 includes 2KB of static RAM memory on-chip (XRAM) plus 256B of internal
RAM in the MPU core. The 2KB of static RAM are used for data storage during normal MPU operations.
CE DRAM: The CE DRAM is the working data memory of the CE (128 32-bit words). The MPU can read
and write the CE DRAM as the primary means of data communication between the two processors.
Rev. 1.1
9
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
