DS_6618_005
78M6618 Data Sheet
1.2 Device Reset
When the RESET pin is pulled high, all digital activity stops. Only the oscillator and RTC module continue
to run. Additionally, all IORAM bits are set to their default states. As long as V1 (the input voltage at the
power fault block) is greater than VBIAS, the internal 2.5 V regulator will continue to provide power to the
digital section.
Once initiated, the reset mode will persist until the reset timer times out. This will occur in 4096 cycles of
the crystal clock after RESET goes low, at which time the MPU will begin executing its preboot and boot
sequences from address 0x0000.
1.3 Power Management
1.3.1 Voltage Regulator
The 78M6618 provides an on chip voltage regulator to create a 2.5V supply for the digital logic. This
regulator can be run off of the V3P3SYS or VBAT inputs depending upon power availability.
1.3.2 Power Fault Management
The 78M6618 includes both hardware and software controlled power fault management. V1 is connected
to a comparator to monitor system power fault conditions. When the output of the comparator falls
(V1<VBIAS) the device will enter BROWNOUT mode if there is sufficient voltage on VBAT. If there is not
sufficient voltage on VBAT then the part will enter RESET mode.
1.3.3 BROWNOUT
In BROWNOUT mode the AFE, CE and other analog circuits are disabled leaving only the non-metering
digital circuits running. The MPU is reduced to the crystal clock rate (32kHz). From BROWNOUT the
78M6618 SW may choose to voluntarily enter other power management modes. See the 78M6618
Programmer’s Reference Manual for more information regarding the programmability of the 78M6618
power management modes. If the overhead on VBAT is insufficient to maintain the BROWNOUT mode
then the device will attempt to enter SLEEP mode. If power is restored the device will return to normal
(mission mode) operation once the PLL has settled.
1.3.4 SLEEP Mode
SLEEP mode provides the savings in battery current as only the Oscillator, and RTC functions are active.
As the CPU is disabled in SLEEP, the device can only wake up from SLEEP by the restoration of power
or RTC autowake.
1.4 Analog Front End (AFE)
The AFE functions as a data acquisition system, controlled by the MPU. The main blocks in the AFE
consist of an input multiplexer, a delta-sigma A/D converter, a FIR(Finite Impulse Response) filter and a
voltage reference. The metrology input signals (IAIH, VA, VB, VBAT and TEMP) are multiplexed before
being sampled by the ADC. The ADC output is decimated by the FIR filter and the results are stored in
XRAM where they can be accessed by the CE and the MPU. The AFE is programmable for various
system requirements including but not limited to:
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Programmable Input Multiplexer settings
Voltage reference, Battery and Temperature monitors inputs
Programmable ADC sampling rate
Programmable FIR length/resolution
Rev. 1.4
7
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
