73S8024RN Data Sheet
DS_8024RN_020
Figures
Figure 1: 73S8024RN Block Diagram .......................................................................................................... 2
Figure 2: Activation Sequence – RSTIN Low When CMDVCC Goes Low ................................................ 10
Figure 3: Activation Sequence – RSTIN High When CMDVCCB Goes Low ............................................. 11
Figure 4: Deactivation Sequence ............................................................................................................... 12
Figure 5: Timing Diagram – Management of the Interrupt Line OFF ......................................................... 13
Figure 6: I/O and I/OUC State Diagram...................................................................................................... 14
Figure 7: I/O – I/OUC Delays Timing Diagram ........................................................................................... 14
Figure 8: 73S8024RN – Typical Application Schematic............................................................................. 15
Figure 9: 20QFN Mechanical Drawing ....................................................................................................... 21
Figure 10: 20QFN Pin Out.......................................................................................................................... 22
Figure 11: 32QFN Mechanical Drawing ..................................................................................................... 23
Figure 12: 32QFN Pin Out.......................................................................................................................... 24
Tables
Table 1: Choice of VCC Pin Capacitor........................................................................................................... 9
Table 2: Card Clock Frequency.................................................................................................................... 9
4
Rev. 1.8
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
