DS_8023C_019
73S8023C Data Sheet
2 System Controller Interface
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The CS (chip select) input allows multiple devices to operate in parallel. When CS is high, the system
interface signals operate as described. When CS is taken low, the system interface signals are
latched internally. The pins I/OUC, AUX1UC, and AUX2UC are weakly pulled up and the OFF signal
is put into a high impedance state.
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•
The CLKSEL signal selects between synchronous and asynchronous operation. When CLKSEL is
low, asynchronous operation is selected. When CLKSEL is high, synchronous operation is selected.
Digital inputs allow direct control of the card interface from the host as follows:
.
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Pin CMDVCC: When set low, starts an activation sequence if a card is present.
Pin 5V/#V: Defines the card voltage.
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The card I/O and Reset signals have their corresponding controller I/Os to be connected directly to
the host:
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Pin RSTIN: controls the card RST signal. When enabled by the sequencer, RST is equal to
RSTIN for both synchronous and asynchronous modes.
.
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Pin I/OUC: data transfer to card I/O contact.
Pins AUX1UC and AUX2UC (auxiliary I/O lines associated to the auxiliary I/Os which are
connected to the C4 and C8 card connector contacts).
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Two digital inputs control the card clock frequency division rate: CLKDIV1 and CLKDIV2 define the
card clock frequency from the input clock frequency (crystal or external clock). The division rate is
defined as follows:
CLKDIV2
CLKDIV1
CLK
0
0
1
1
0
1
0
1
⅛ XTAL
XTAL
¼ XTAL
½ XTAL
When the division rate is equal to 1 (CLKDIV2 =0 and CLKDIV1 = 1), the duty-cycle of the
card clock depends on the duty-cycle and waveform of the signal applied on the pin XTALIN.
When other division rates are used, the 73S8023C circuitry guarantees a duty-cycle in the
range 45% to 55%, conforming to ISO-7816-3 and EMV 4.1 specifications.
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Interrupt output to the host: As long as the card is not activated, the OFF pin informs the host about
the card presence only (low = no card in the reader). When CMDVCC is set low (Card activation
sequence requested from the host), a low level on OFF means a fault has been detected (e.g. card
removedl during a card session, or voltage fault, or thermal / over-current fault) that automatically
initiates a deactivation sequence.
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Power Down: The PWRDN pin is a digital input that allows the host controller to put the 73S8023C in
its Power Down state. This pin can only be activated outside of a card session.
The CLKOUT signal is a buffered output of the signal applied to the XTALIN pin whether it is an
external clock source or it is configured as a crystal oscillator. CLKOUT can be used when using
multiple 73S8023C devices to share a single clock signal.
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The STROBE input directly drives the smart card CLK signal when operating in synchronous mode.
STROBE is ignored in asynchronous mode.
Rev. 1.5
7
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
