73S8023C Data Sheet
DS_8023C_019
1.4 Microcontroller Interface
Name
Pin
Description
CMDVCC
18
Command VCC (negative assertion): Logic low on this pin causes the DC-DC
converter to ramp the VCC supply to the card and initiates a card activation
sequence.
5V/#V
31
5
5 volt / 3 volt card selection: Logic one selects 5 volts for VCC and card
interface, logic low selects 3 volt operation. When the part is to be used with
a single card voltage, this pin should be tied to either GND or VDD. However,
it includes a high impedance pull-up resistor to default this pin high (selection
of 5V card) when unconnected
PWRDN
Power Down control input: Active High. When Power Down (PD) mode is
activated, all internal analog functions are disabled to place the 73S8023C in
its lowest power consumption mode. The PD mode is allowed only out of a
card session (PWRDN high is ignored when CMDVCC = 0). Must be tied to
ground when power down function is not used.
CLKDIV1
CLKDIV2
29
30
Sets the divide ratio from the XTALIN oscillator (or external clock input) to the
card clock. These pins include pull-down resistors.
CLKDIV1
CLKDIV2
Clock Rate
0
0
1
1
0
1
1
0
XTALIN/8
XTALIN/4
XTALIN/2
XTALIN
OFF
22
Interrupt signal to the processor: Active Low. Multi-function indicating fault
conditions and card presence. Open drain output configuration; it includes an
internal 20 kΩ pull-up to VDD.
RSTIN
I/OUC
19
26
Reset Input: This signal controls the RST signal to the card.
System controller data I/O to/from the card. Includes internal pull-up resistor
to VDD.
AUX1UC
AUX2UC
CS
27
28
8
System controller auxiliary data I/O to/from the card. Includes internal pull-up
resistor to VDD.
System controller auxiliary data I/O to/from the card. Includes internal pull-up
resistor to VDD.
When CS = 1, the control and signal pins are configured normally. When CS
is set low, signals CMDVCC, RSTIN, PWRDN, 5V/#V, CLKDIV1, CLKDIV2,
CLKSEL are latched. I/OUC, AUX1UC, and AUX2UC are set to high
impedance pull-up mode and won’t pass data to or from the smart card. OFF
output is tri-stated.
CLKSEL
16
Selects CLK and RST operational mode. When CLKSEL is low (default), the
circuit is configured for asynchronous card operation and the sequencer
manages the control of CLK and RST. When CLKSEL is high, the signal
CLK is a buffered copy of STROBE and the signal RST is directly controlled
by RSTIN.
STROBE
CLKOUT
25
32
When CLKSEL = 1, the signal CLK is controlled directly by STROBE.
CLKOUT is the buffered version of the signal on pin XTALIN.
6
Rev. 1.5
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
